AMD Data Center Roadmap: 4th Gen EPYC Genoa-X and the company’s first Data Centre APU MI300X Steals the Show

At their Financial Analyst Day 2022, AMD highlighted its CPU server roadmap, as well as 4th-Gen EPYC Genoa-X processors with 3D V-Cache, the edge and telecommunications-focused EPYC Siena, and AMD’s first data centre APU, the MI300X. In addition, AMD hinted at the release of the 5th-generation EPYC Turin processors before the end of 2024.

The 4th-Gen EPYC family’s server CPU roadmap demonstrates a major increase in AMD’s target markets. All of these chips feature the Zen 4 microarchitecture. AMD’s baseline EPYC Genoa silicon will now be available in general-purpose server chips, as well as a high-performance optimised EPYC Genoa-X with 3D V-Cache, cloud-optimized chips with the 128-core 256-thread Bergamo, and an edge- and telecommunications-focused Siena processors. All of the Zen 4 chips, it appears, will fit into the same SP5 socket.

AMD revealed that the 5th-generation EPYC Turin family will be available in 2024, but provided no other information

Turin will be available in 4nm and 3nm processes, as well as 3D V-Cache and cloud-optimized versions, according to the CPU core roadmap. In a Java SPECjbb benchmark, AMD demonstrated a 96-core EPYC Genoa that outperformed the current-gen EPYC flagship by more than 75%. The transition to the 5nm Zen 4 architecture, as well as the 12-channels of DDR5 memory, account for this increase. Not to mention the extra 32 cores above the EPYC from the prior generation. Genoa also supports PCIe 5.0 and CXL-attached memory, which Samsung’s 512GB CXL memory Expander demonstrates. Genoa is expected to ship in the fourth quarter of this year, according to AMD.

The 128-core Bergamo has been optimised for density and scale-out, with up to 128 Zen 4c cores and an incredible 256 threads in a single socket. Bergamo uses the same SP5 socket as the Genoa CPUs and supports the Zen 4 ISA in its entirety.

The Zen 4c cores are theoretically comparable to the efficiency cores (e-cores) used in other chip designs, including Arm and x86. These ‘c’ cores are smaller than the conventional Zen 4 core that will be introduced in Genoa, with some superfluous functionality removed to increase computation density. To improve core counts, the chips offer a density-optimized cache hierarchy, which addresses cloud applications that require higher thread density. 

This could indicate that the chips have a lower cache or that a cache level has been eliminated, but AMD has not provided any additional information. The Zen ‘c’ cores support the entire Zen 4 ISA, unlike Intel’s Alder Lake, and AMD will not disable functionality such as AVX.

AMD has announced that a variant of its future EPYC Genoa processors will include up to 1 GB of L3 cache

The 5nm Genoa-X processors will have up to 96 cores and will fit into the same socket as the standard Genoa CPUs. In effect, these are the Zen 4 equivalents of the EPYC Milan-X CPUs with 3D V-Cache.

The AMD Instinct MI300 is the company’s first APU for the data centre, featuring both x86 CPU and GPU cores on the same chip package. AMD’s 4th-generation AMD Infinite Architecture uses a coherent memory interface to connect the Zen 4 CPU cores and CDNA 3 GPU cores.

The processor features 3D packaging technology, with the CPU, GPU, cache, and HBM all packed into a single chip, however, it’s unclear whether all of these components are stacked vertically or simply some of them are. In AI applications, AMD estimates that this accelerator can deliver up to an 8X performance boost over the MI250X.

also read:

AMD Phoenix Point 4nm APUs with Zen 4 and RDNA 3 cores will be available in 2023, followed by Strix Point with Zen 5 and RDNA 3+ cores in 2024

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