Sunday, May 29, 2022

AMD’s EPYC Genoa CPU With 12 Next-Gen Zen 4 CCDs appear online in leaked images

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The first image of the EPYC Genoa CPU in its full-fat 12 Zen 4 CCD version has been released just one day after AMD’s SP5 socket was revealed. The image was uncovered by @phatal187 in the TF AMD Microelectronics magazine and displays an undisclosed AMD EPYC Genoa CPU without its enormous heat spreader. While we don’t know how many of the 12 CCDs are enabled on this part, such combinations will offer up to 96 cores and 192 threads. The enormous IO die, as well as a large number of capacitors on the interposer, will all fit inside the massive LGA 6096 package.

With recent speculations claiming that the consumer-targeted Zen 4 CPUs will go into mass production later this month, it appears that the EPYC Genoa CPUs will follow suit, with an official debut set for the second half of 2022.

EPYC Genoa is compatible with SP5 platform

To begin with, AMD has already stated that EPYC Genoa would be compatible with the new SP5 platform, which includes a new socket, and that SP3 compatibility will be available until EPYC Milan. New memory and capabilities would be supported by the EPYC Genoa CPUs. According to the newest information, the SP5 platform will also include a completely new socket with 6096 pins grouped in the LGA (Land Grid Array) configuration. With 2002 more pins than the present LGA 4094 socket, this will be AMD’s largest rocket ever.


The socket will support AMD’s EPYC Genoa processor as well as future EPYC models. AMD will have to squeeze more cores into its EPYC Genoa CPU box to reach 96 cores. AMD claims to have achieved this by including up to 12 CCDs in their Genoa chip. The Zen 4 architecture will be used to power each CCD, which will have eight cores. We could be looking at a big CPU interposer, even larger than the present EPYC CPUs if this corresponds with the increased socket size. The CPU is believed to have a TDP of 320W, which may be increased to 400W.

Aside from that, AMD’s EPYC Genoa CPUs will have 128 PCIe Gen 5.0 lanes, with 160 available in a 2P (dual-socket) configuration. The SP5 platform will also enable DDR5-5200 memory, which is a significant upgrade above the current DDR4-3200 MHz DIMMs. Not only that, but it will also support up to 12 DDR5 memory channels with two DIMMs per channel, allowing for up to 3 TB of system memory with 128 GB modules.

Furthermore, a leaked AMD slide shows that future EPYC SOCs would support DDR5 pin speeds of up to 6000-6400 Mbps. This is most likely referring to Turin or Bergamo, as they are the successors to Genoa.

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Nivedita Bangari
Nivedita Bangari
I am a software engineer by profession and technology is my love, learning and playing with new technologies is my passion.


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