According to a statement made by AMD to Tom’s Hardware, reports that AMD’s rDNA 3 GPUs have defective shader pre-fetch functionality is false. AMD’s announcement follows media claims that the recently released Navi31 technology in the RDNA 3 graphics cards contains ‘non-working shader pre-fetch circuitry.’ @Kepler L2 provided code from the Mesa3D drivers that looked to imply the shader pre-fetch doesn’t work for some GPUs with the A0 revision of the hardware (CHIP GFZ1100, CHIP GFX1102, and CHIP GFZ110).

“Like previous hardware generations, shader pre-fetching is supported on RDNA 3 as per [gitlab link]. The code in question controls an experimental function that was not targeted for inclusion in these products and will not be enabled in this generation of products. This is a common industry practice to include experimental features to enable exploration and tuning for deployment in a future product generation.” — AMD Spokesperson to Tom’s Hardware.

According to AMD’s comment, the code cited by Kepler L2 related to an experimental function that was not planned for the final RDNA 3 products, hence it is deactivated for the time being. AMD points out that integrating experimental features in new silicon is a very standard procedure, which is correct – we’ve seen this strategy employed with other types of processors, such as CPUs.

For example, AMD sold an entire generation of Ryzen 3000 products with the TSVs required to enable 3D V-Cache but didn’t use the technology until the Ryzen 5000 era was over. Similarly, Intel frequently adds features that may or may not be included in the final product, with its DLVR functionality being a recent example.

Naturally, one would anticipate that if an ‘experimental’ feature works flawlessly, it will be incorporated into the final product if no additional accommodations are required (like the additional L3 cache slice needed for 3D V-Cache). As a result, the distinction between an ‘experimental’ or ‘good to have but not critical or required to hit targets’ feature may be blurred. In either instance, AMD claims that the pre-fetch method works well on RDNA 3.

The second elephant in the room is AMD’s usage of an A0 stepping of the RDNA 3 silicon, which means this is the chip’s first physically unaltered version. This has led to rumors that AMD is shipping ‘unfinished silicon,’ but such conjecture is unfounded.

AMD would not comment on our questions about whether it used A0 silicon for the first wave of RDNA 3 CPUs, although industry sources say it did with Navi31.

According to our sources, the corporation launched with A0-revision silicon for practically all of the 6000 series and the majority of the 5000 series. This does not imply an ‘unfinished product.’ All design teams strive to get the design right on the first go with working, shippable silicon. Nvidia, for example, frequently ships A0 stepping silicon as well.

Throughout their lives, microprocessors can go through multiple versions, often to cure flaws or errata and/or increase performance. In general, the first revision of silicon from the fabs is A0, and subsequent minor respins (changes to the metal layer) are A1, A2, and so on. Silicon modifications cause the move to a ‘B’ or a subsequent letter, and so on. As the chip is developed, this will be repeated with updated alpha-numeric designators.

Almost all sophisticated chips have known and undiscovered errata and flaws, which are addressed with firmware, driver, and software workarounds that can decrease or remove those issues, and they ship that way – it’s the essence of current semiconductor design and manufacture. For example, Intel’s Skylake chip generation launched with 53 known errata, then six months later, Intel announced an additional 40 errata. This is prevalent since semiconductor design cycles are often years long, leaving little time to respin the chip to solve small faults. We notice similar trends with different processor types and generations.

Making chips is difficult; they are the most advanced class of electronics ever built by humanity, but they have nearly unimaginable little features. As a result, difficulties and errors may arise, necessitating further updates. Pay little attention to those who assert that an A0 stepping always means ‘unfinished silicon.’ Success is judged by the delivery of functional silicon that fulfills targets on the first try.

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