The Intel Xeon CPU Max Series is the first x86 CPU in the world to support HBM memory, according to Intel. This product line, which we’ve previously called Sapphire Rapids, will contain 56 performance cores (112 threads), a 350W TDP, and other specifications. There are four clusters in its EMIB-based design. It also has 64 GB of HBM2e memory split into 4x clusters of 16 GB for a net total of 1 TB/s memory bandwidth and more than 1 GB of HBM per core, which is perhaps the most intriguing aspect of the system.
Coincidentally, the Aurora supercomputer at Argonne National Laboratory will be driven by this CPU. These will also be delivered to Kyoto University and the Los Alamos National Laboratory. According to Intel, the addition of HBM memory won’t require any code modifications and should be completely transparent to the user.
The four tiles that make up the 56 cores, formerly known as Sapphire Rapids, are coupled via Intel’s multi-die interconnect bridge (EMIB). The package includes 64GB of HBM, and the platform will support PCIe 5.0 and CXL 1.1 I/O.
- 68% less power usage than an AMD Milan-X cluster for the same HCPG performance.
- AMX extensions boost AI performance and deliver 8x peak throughput over AVX-512 for INT8 with INT32 accumulation operations.
- Provides flexibility to run in different HBM and DDR memory configurations.
- Climate modeling: 2.4x faster than AMD Milan-X on MPAS-A using only HBM.
- Molecular dynamics: On DeePMD, 2.8x performance improvement against competing products with DDR5 memory.
The company’s codenamed Ponte Vecchio architecture originally revealed in 2019 and subsequently detailed in 2020–2021, will be used by Intel’s Data Center GPU Max computing GPU family. The Ponte Vecchio CPU from Intel contains approximately 100 billion transistors (not including memory), spread across 47 tiles, making it the most complex processor ever made (including 8 HBM2E tiles). As different tiles are produced by other manufacturers using various process methods, the product also extensively employs Intel’s advanced packaging technologies (such as EMIB).
The 512-bit vector and 4096-bit matrix (tensor) engines are supported by Intel’s Data Center GPU Max compute GPUs, which are based on the company’s Xe-HPC architecture, which is specifically designed for AI and HPC applications.
Xe-HPC has far more advanced memory and caching subsystems, differently configured Xe cores, and other improvements than Xe-HPG (each Xe-HPG core features 16 256-bit vector and 16 1024-bit matrix engines, whereas each Xe-HPC core sports eight 512-bit vector and eight 4096-bit vector engines). Additionally, Xe-HPC GPUs lack texturing units and render back ends, making it impossible for them to generate graphics conventionally. Surprisingly, ray tracing is supported by Xe-HPG for visualization on supercomputers.
One of the key components of Xe-HPC is Intel’s Xe Matrix Extensions (XMX), which, according to Intel, allow the Data Center GPU Max 1550 to achieve very impressively tensor/matrix performance of up to 419 TF32 TFLOPS and up to 1678 INT8 TOPS. Of course, the peak performance figures supplied by computing GPU developers are significant, but they might not accurately represent the performance that can be obtained on actual supercomputers for actual applications.
However, we cannot help but notice that Intel’s top-of-the-line Ponte Vecchio is consistently outperformed by AMD’s Instinct MI250X, except for FP32 Tensor, where it lags far behind Nvidia’s H100 (TF32). According to Intel, the Data Center GPU Max 1550 is 1.5 times faster than Nvidia’s A100 for NekRS virtual reactor simulations and is 2.4 times faster than Nvidia’s A100 on Riskfuel credit option pricing.
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