Zen 3 to bring 10-15% IPC gains per thread & 32 MB of shared L3 cache, Zen 4 to feature 1 MB L2 cache & AVX 512 support

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AMD will be launching their 7nm++ Zen 3 based Ryzen 4000 CPUs this year. Even though Zen 3 belongs to the optimization phase of AMD’s inflection-optimization cycle, it will do bring some core architecture enhancements than last-gen.

The latest report from AdoredTV suggests the IPC gains in Zen 3 will be on par with that of Zen 2 architecture, which is likely to be around 10-15% per thread. We can also expect higher multi-threaded performance from Zen 2 due to the IPC gains.

Zen 3 to bring 10-15% IPC gains per thread & 32 MB of shared L3 cache, Zen 4 to feature 1 MB L2 cache & AVX 512 support

The Zen 3 architecture will feature a new CCX design, which could be among those core architecture improvements which was told by AMD CEO Dr. Lisa Su. Zen 3 will have one CCX per eight cores with a single L3 cache at 32 MB per CCX while Larger cache memory of 48 MB or 64 MB are not indicated.

With the new cache design and increased number of cores there’s access to a common L3 cache on the same die. This will tend to reduce latency and improve gaming performance, also the Zen 3 will continue to use SMT-2 and not SMT-4.

According to the new information about the 5nm Zen 4 based Ryzen 4000 CPUs, it is likely to feature more cores, a 1 MB L2 cache, AVX 512 support, and will obviously even better IPC gains due to the jump to 5nm process.

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