In 2025, the Taiwan Semiconductor Manufacturing Company (TSMC) will start mass-producing semiconductors using its 2-nanometer process, according to a recent report from Taiwan. The timetable corresponds to the one that TSMC’s management has frequently provided during analyst conferences.

Additionally, these rumours state that TSMC is preparing to launch N2P, a new 2-nanometer node, the following year after N2. Although TSMC has not yet officially endorsed a new process known as N2P, it has adopted a name resembling this for its existing 3-nanometer semiconductor technologies, with N3P being an improved version of N3 and reflecting improvements in the manufacturing process.

According to a report from Taiwanese supply chain sources released today, mass production of 2-nanometer semiconductors by TSMC is proceeding as planned.

A conference in 2021 during which the company’s chief executive Dr. C.C. Wei stated that his company is confident about 2-nanometer mass production in 2025 was one instance where the company’s executives provided an outline of the timeline for the next-generation manufacturing process.

The timeline has since been confirmed by the TSMC’s senior vice president for research, development, and technology, Dr. Y.J. Mii, and Dr. Wei’s most recent statement on the subject came in January, when he said that the process was “ahead of schedule” and would enter the test production stage in 2024.

These claims are supported by the most recent rumours, which also state that mass production will take place at the Taiwan Semiconductor Manufacturing Company’s factories in Baoshan, Hsinchu. The Hsinchu plant is TSMC’s top choice for the cutting-edge technology, and the company is also constructing a second facility in Taichung, Taiwan. The management of this facility, known as Fab 20, confirmed its construction in 2021, when the business purchased the plant’s land.

The report also mentions an alleged N2P process, which is an intriguing detail. The N2 process node has not yet received the same information from the fab, despite the Taiwan Semiconductor Manufacturing Company having confirmed a high-performance N3 variant known as N3P. According to sources in the supply chain, N2P will employ BSPD (back-side power delivery) to enhance performance.

Making semiconductors is a difficult process. Even though producing transistors thousands of times smaller than a human hair frequently receives the most attention, other equally challenging areas prevent chip makers from improving chip performance.

The wires on a silicon piece are one such area. Due to the transistors’ tiny size, connecting wires must also be very small in order to connect them to a power source. The location of these wires is a significant obstacle for new process technologies. The wires are typically positioned above the transistors in the first iteration of a process, and below in later iterations.

The latter procedure, known as BSPD, is a development of what is known as through silicon vias in the industry (TSVs). TSVs are wafer-through connections that enable the stacking of numerous semiconductors, including memory and processors. Bonding the wafers together forms a BSPDN (back-side power deliver network), which increases power efficiency by delivering current to the chip through the backside, which is more suited and has lower resistance.

Investment bank Morgan Stanley predicts that TSMC’s revenue will decrease by 5% to 9% during the second quarter, despite rumours suggesting new process technologies. The most recent report from the bank raises the anticipated decline, which was initially anticipated to be 4% quarter over quarter. An order reduction from smartphone chip companies is what caused the dip.

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