AMD just crossed a milestone the entire semiconductor industry has been watching. AMD has begun production ramp of its 6th Gen AMD EPYC CPUs, codenamed “Venice,” on TSMC’s advanced 2nm process technology — making Venice the first high-performance computing product in the industry to enter production on TSMC 2nm.
Read the full official announcement at AMD’s investor relations page.
This announcement, released May 21, 2026, alongside the Red team’s $10 billion Taiwan ecosystem investment, confirms that Venice is not a roadmap promise — it is a chip in production today.
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Why “First HPC Product on TSMC 2nm” Matters
Process node transitions are the most consequential moments in semiconductor history. Each generation delivers meaningful gains in performance per watt, transistor density, and ultimately cost per compute unit at scale.
TSMC’s 2nm node — also known as N2 — is the most advanced commercial fabrication process available anywhere in the world. The fact that AMD, not Intel’s or NVIDIA’s next-generation designs, holds the distinction of being the first HPC product to enter volume production on N2 is a direct statement about where AMD sits in TSMC’s production priority queue — and about the maturity of AMD’s design execution.
The milestone in the execution of the AMD data centre CPU roadmap demonstrates continued progress toward delivering the leadership performance and energy efficiency required for next-generation cloud, enterprise, and AI infrastructure.
TSMC’s CEO Speaks Directly
Dr. C.C. Wei, Chairman and CEO of TSMC, said: “We are pleased to see AMD continue to make strong progress with its next-generation EPYC processor on our advanced 2nm process technology. Our close collaboration with AMD reflects the importance of pairing leadership process technology with advanced design innovation to enable the next era of high-performance and AI computing.”
A personal statement from TSMC’s CEO on a customer’s production ramp is rare. It signals the depth of the AMD-TSMC partnership — and the commercial significance of Venice to TSMC’s own 2nm volume ramp.
Production in Taiwan Today, Arizona Tomorrow
Venice is ramping production in Taiwan, with future plans to ramp production at TSMC’s Arizona fabrication facility. By pairing next-generation EPYC processor innovation with advanced manufacturing capacity across the globe, AMD is expanding the foundation needed to support customers as they deploy and scale AI infrastructure.
The Arizona ramp is geopolitically significant. US-based advanced semiconductor production remains a national priority under both CHIPS Act funding and ongoing trade policy. AMD shipping Venice from TSMC Arizona — when that fab comes online for 2nm — gives hyperscalers and government customers a US-domestic supply option for the most advanced server CPUs available anywhere.
Why Venice Matters for Agentic AI
As AI adoption expands from training and inference to increasingly complex agentic workloads, the CPU is becoming even more critical to scaling AI infrastructure — coordinating data movement, networking, storage, security, and system orchestration across the data centre.
This is the framing that matters for 2026 and beyond. The GPU does the heavy compute. The CPU does everything else — scheduling agent tasks, managing memory, orchestrating networking, running security checks, handling storage I/O. In the agentic AI era, where Claude Managed Agents, AMD Ryzen AI Halo, and enterprise AI systems run continuous multi-step workflows rather than single inference calls, CPU performance and efficiency under sustained load becomes a first-order concern again.
Venice on 2nm — with the EFB advanced packaging confirmed in AMD’s simultaneous $10 billion Taiwan announcement — is AMD’s answer to that demand.
Introducing Verano — Venice’s Follow-On Is Already Planned
AMD also plans to extend TSMC’s 2nm process technology across its data centre CPU roadmap with “Verano” — a 6th Gen EPYC processor optimised for performance-per-dollar-per-watt leadership. Designed to support cloud and AI computing workloads, Verano is expected to build on the AMD EPYC platform with advanced memory innovations, including LPDDR, to deliver the CPU performance, bandwidth, and efficiency required for increasingly power-constrained workloads and applications.
The Verano announcement is a deliberate signal to hyperscalers evaluating multi-year infrastructure commitments: AMD’s 2nm roadmap does not stop at Venice. Verano’s LPDDR integration is specifically called out as an answer to the memory bandwidth demands of agentic AI workloads — the same demand that is driving global memory shortages and smartphone price hikes across the industry.
Venice + Helios + MI450X — The Full Picture
Venice does not ship in isolation. It is the CPU foundation of the AMD Helios rack-scale platform announced simultaneously, paired with AMD Instinct MI450X GPUs, advanced EFB packaging, and the ROCm open software stack. Together, they represent AMD’s most complete AI infrastructure answer to NVIDIA’s Blackwell-based NVL rack systems.
| Component | Status |
|---|---|
| EPYC “Venice” CPU | Production ramp — TSMC 2nm, Taiwan |
| EPYC “Venice” — Arizona | Future ramp, TSMC Arizona fab |
| EPYC “Verano” CPU | Planned, LPDDR-integrated follow-on |
| AMD Instinct MI450X GPU | Helios deployment, H2 2026 |
| AMD Helios Platform | Multi-gigawatt deployments, H2 2026 |
| EFB Packaging | Qualified, ASE/SPIL/PTI |
The Bottom Line
Lisa Su said: “Ramping Venice on TSMC 2nm process technology marks an important step forward in accelerating the next generation of AI infrastructure. As AI and agentic workloads scale rapidly, customers need platforms that can move from innovation to production faster. Our deep partnership with TSMC is helping AMD bring leadership compute technologies to market with the speed and scale required to meet this moment.”
Being first to production on TSMC’s 2nm is not a coincidence — it is the outcome of years of design discipline, deep foundry partnership, and a server CPU roadmap that has never missed a scheduled node transition. Venice in production today’ means Helios deployments at a multi-gigawatt scale in H2 2026 are backed by real silicon, not projections.
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