Samsung is advancing significantly in the realm of AI chip design, both through independent efforts and strategic collaborations within the industry. In a noteworthy alliance, Samsung has partnered with Naver, a prominent South Korean tech company, to embark on a joint venture aimed at developing a new artificial intelligence chip. This commitment to the initiative spans over a year and signifies a concerted effort to push the boundaries of AI chip technology.
All About the New Chip from Samsung and Naver
The primary thrust of this collaborative endeavor has been the enhancement of power efficiency within the designed chip. Notably, the chip is purported to demonstrate an impressive 8-fold increase in power efficiency compared to rival chips, particularly those emanating from the stables of NVIDIA, a company renowned for establishing the gold standard in AI chip development.
The collaborative journey between Samsung and Naver was set into motion with the signing of a Memorandum of Understanding (MOU) in December of the preceding year. The shared objective was to delve into the development of AI semiconductors and to translate this vision into reality, a dedicated task force was established. The culmination of this collaborative effort materialized with the unveiling of the AI chip at an event hosted by the Ministry of Science and ICT in Seoul.
Categorized as a Field-Programmable Gate Array (FPGA), the newly developed chip affords developers the flexibility to make alterations to the design, a crucial feature typically employed during the prototyping phase before mass production. This chip has been finely tuned for “inference,” a critical aspect of AI models where logical outcomes are generated following the completion of the learning phase.
The distinguishing feature of this chip lies in its exceptional power efficiency, as asserted by Naver. The claim is that the chip showcases an 8-fold improvement in power efficiency when compared to counterparts from NVIDIA. This remarkable achievement has been facilitated by the strategic integration of low-power Dynamic Random-Access Memory (DRAM), thereby enhancing overall efficiency and enabling the chip to deliver comparable computational performance with significantly lower power consumption.
