AMD Ryzen 8000 Strix Point APU configurations

AMD’s next-generation Strix Point APUs will be available in two configurations based on Zen 5 and Zen 5C cores. Several rumours and leaks have surfaced recently regarding AMD’s next-generation Ryzen 8000 APU family, codenamed Strix Point. According to AMD’s official roadmap, the Strix Point family will feature Zen 5 CPU cores, RDNA 3.5 GPU cores, and an improved AI engine. According to rumours, AMD’s Strix Point range will be available in two flavours: a regular monolithic design and a chiplet series.

AMD Strix Point Monolithic APUs will be similar to Phoenix APUs in that they will have all core IPs and I/O on the same die.

AMD
credit: wccftech

AMD changed a few things with Phoenix, and the company just acknowledged that a number of its entry-level Ryzen 7040 APUs have a hybrid design, with both Zen 4 and Zen 4C cores. The Strix Point Monolithic dies are now expected to use the same design. According to @Olrak29_, the Strix Point Mono CPUs will include 4 Zen 5 cores and 8 Zen 5C cores for a total of 12 cores and 24 threads.

A newly disclosed APU may have used the same configuration, as it also had 12 cores and 24 threads. Aside from that, we may expect AMD to include their RDNA 3.5 GPU cores as well as a variety of I/O on the same device. A recent LLVM patch also revealed that the GFX1150 and 1151 IDs are reserved for Strix Point and Strix Point Halo APUs. The APUs will most likely be released as part of the Ryzen 8050 series (Ryzen 8000 APU range).

The AMD Ryzen 8000 Strix Halo APU series will also include 16 Zen 5 cores. These chips will have a twin Zen 5 CCD architecture with 8 cores each, and they are expected to use some type of 3D V-Cache in the future. While the Strix Point Halo APUs appear to be quite similar to the Granite Ridge “Ryzen 8000” Desktop series, the IOD (IO Die) may be slightly different, according to Kopite7kimi. The iGPU for the Raphael APUs is located within the IOD, and the same may be true for the Granite Ridge and Strix Point Halo APUs.

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