Yesterday marked the official release of AMD EPYC 9004 “Genoa,” the company’s 4th Generation data centre CPU lineup with the newest Zen 4 core architecture. The AMD EPYC 9004 Genoa series marks the beginning of the EPYC brand’s new server ecosystem. It covers a wide range of sectors, families, and families.
Three families will make up the AMD Zen 4 range for data centres: the regular Zen 4 for EPYC Genoa, the compute density-optimized Zen 4C for EPYC Bergamo, and the cache-optimized Zen 4 V-Cache for the EPYC Genoa-X series. Additionally, the portfolio will include an affordable entry-level server option called EPYC Siena that will have the same Zen 4 cores as SP5, but on a brand-new platform called SP6 that will again place a greater emphasis on TCO optimization. The EPYC 8004 family will serve as the brand name for the lineup.
The Ryzen 7000 and Radeon 7000 products use the same 5nm Chiplet architecture as the AMD EPYC 9004 Genoa “Zen 4” CPUs. IPC increases by 14% thanks to the CPU or 1% more than Zen 4 consumer parts. The geomean data, which spans a wider range of workloads than the Ryzen CPUs’ consumer-centric workloads, is the cause of the modest improvement. The 4th Gen FinFET technology increased metal stack, and performance-enhancing design is used in the 5nm process node.
Up to 12 CCDs, 96 cores, and 192 threads are included in the standard Zen 4 lineup. 32 MB of L3 cache and 1 MB of L2 cache are provided with each CCD. The AVX-512 (256b data route), BFLOAT16, VNNU, addressable memory of 57b/52b, and an improved IOD with an internal AMD Gen3 Infinity Fabric architecture with increased bandwidth will all be included in the EPYC 9004 CPUs (die-to-die interconnect). For quick CPU connectivity, this offers up to four 32 Gb/s socket-to-socket fabrics. A 1.9x improvement over the Infinity Fabric design from the previous generation.
AMD compared an Ice Lake-SP (Sunny Cove) core and its L2 cache to its Zen 4 core and its L2 cache. According to the facts, Genoa offers 40% less area than the competitors while giving a 48% higher energy efficiency.
With up to 96 cores, 192 threads, and 384 MB of L3 cache, the highest components are based on a 12 CCD SKU. These SKUs will have TDPs ranging from 360W to 400W. Next up are the 8 CCD SKUs, which offer a total of 16 SKUs with core counts ranging from 16 to 64. These chips have TDPs of 280/320/360W and 256 MB of L3 cache. Last but not least, there are the 4 CCD SKUs, which feature 4 SKUs with 16–32 cores each. These chips will have TDPs between 200 and 210 Watts and 64 to 128 MB of L3 cache.
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