As we saw in the leaked benchmarks a few days ago, AMD’s EPYC Genoa CPUs are going to provide some insane performance improvements for the x86 server market. Now, we get to see an even better performance teaser in the form of the cache and latency benchmarks for the top EPYC 9654 CPU, which rocks up to 96 cores and destroys the AMD Milan-X CPUs with its enormous inter-cache bandwidth figures.
Yuuki AnS has once again given the cache and latency numbers for both the AMD EPYC 9654 “Genoa” and Intel Xeon Platinum 8480+ “Sapphire Rapids-SP” CPU in the most recent performance benchmarks. You might recall that earlier this year, the same leaker also published the cache and latency numbers for the AMD EPYC Milan-X and an extremely early Sapphire Rapids-SP CPU. Since that time, the red team has begun supplying Milan-X to clients and is preparing to introduce Genoa CPUs, but Intel has not yet introduced its Sapphire Rapids-SP chips, which have been experiencing continual delays.
A sizable Last-Level-Cache was added to the Zen 3 core package or CCD by the AMD EPYC Milan-X.
 By combining the 32 MB of cache offered by each CCD with up to 64 MB of L3 cache per CCD, the Milan-X CPU’s cache was increased by 512 MB for a total of 768 MB. In addition to having more available cache than the regular Milan chips, Milan-X also operates very quickly. By Chips and Cheese, who did an outstanding job of delving deeply into the V-Cache architecture for Milan-X CPUs, we have seen some inter-CPU cache figures.
The AMD EPYC 9654, a Genoa SKU with 96 cores and 192 threads, is the CPU under discussion. With a base speed of 2GHz and a boost clock that varies between 2.15 and 3.7 GHz at a maximum TDP of 360W, this chip was tested in a dual-socket setup. Remember that this is simply an engineering sample and that the final performance might much improve. The leaker claims that the EPYC 9664 is also available, thus this chip isn’t the flagship either. Genoa may be a high-clock optimized chip with a higher TDP because we know that Genoa will have a maximum of 96 cores in a total of 12 CCDs (each with 8 cores).
The Genoa EPYC 9654 CPU from AMD has 384 MB of L3 cache and 96 MB of L2 cache, which is more than Milan-X. (1 MB per core). Thus, there are 480 MB in total, but Genoa will also have a 3D V-Cache variant called Genoa-X the following year, which will have up to 1248 MB of total cache (384 MB L3 + 96 MB L2 + 768 MB V-Cache).
The AMD EPYC 9654 Genoa CPU is a whole different animal in terms of bandwidth, as I said before. The inter-cache figures are insane, and the memory bandwidth is the highest of the three contemporary processors.
In L1 cache testing, the Genoa CPU outperforms Milan-X by 2.2 times and Sapphire Rapids-SP Xeon by 17%. In L2 cache testing, the CPU performs 89 percent better than Milan-X and 2.44 times better than the Xeon it replaces. Last but not least, the Genoa CPU outperforms Milan-X and Xeon parts by an astounding 3.27 and 8.8x, respectively, in L3 bandwidth. That translates to an insane inter-CPU cache bandwidth of up to 30 TB/s.
The 128 PCIe Gen 5.0 lanes on AMD’s EPYC Genoa CPUs will increase to 160 in a 2P (dual-socket) configuration. Additionally, the SP5 platform will handle DDR5-5200 memory, which is a staggering upgrade from the DDR4-3200 MHz DIMMs now in use. Not only that, but it will also support up to 12 DDR5 memory channels, each with a capacity of two DIMMs, allowing for the use of 128 GB modules to provide up to 3 TB of system memory. It is anticipated that the AMD EPYC 9000 Genoa CPU range would go on sale in the second half of this year.
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