Intel announced during its Vision conference in Grapevine, Texas, that its infrastructure processor roadmap will be extended through 2026. IPUs (infrastructure processing units) are mega chips meant to boost data centre efficiency by offloading services like networking control, storage management, and security that were previously performed by the host CPU. Intel is working on IPUs in conjunction with infrastructure providers such as Google and Microsoft.
Sandra Rivera, executive vice president and general manager of the company’s datacenter and AI group, said at CEO Pat Gelsinger’s opening speech on Tuesday that the IPUs will complement Xeon server chips but will also work with chips and accelerators based on other architectures such as Arm.
Mount Evans, Intel’s first IPU, was created in collaboration with Google and will be available this year to Google and other service providers. The 200Gbps ASIC platform is based on Arm Neoverse N1 cores and includes network and storage virtualization offloading functions as well as compatibility for the NVM interface to imitate NVMe devices.
Oak Springs Canyon, a second-generation FPGA-based 200 Gbps IPU based on the Xeon D server CPU and the Agilex FPGA, is also shipping this year. The networking and storage functions of the software-defined platform can be changed. It also includes a crypto block and two 100 Gigabit Ethernet network ports. It will begin delivering to select service providers this year, with broader deployments following next year.
The next-generation 400Gbps components will follow. Mount Morgan, an ASIC IPU, is planned to ship in 2023 or 2024, while Hot Springs Canyon, an FPGA-based IPU, is expected to ship in 2023, with widespread deployments in 2024.
To perform various data center activities, most of the main server chip makers are developing a new class of SmartNIC-type chips. With Arm-based CPU chips and Mellanox networking components, Nvidia’s BlueField data processing unit, or DPU, is available. AMD has hinted that it may create chips using its CPUs with technologies from Xilinx, which it recently purchased, and Pensando, which it is in the process of purchasing.
During a break-out session at Vision, Rakesh Cheerla, director of software product management at Intel, noted that trends like machine learning and the metaverse are driving the development of IPUs
The programmes are divided into microservices and deployed over thousands of nodes. The hardware provides raw processing capabilities, but the software allows for scaling, which is critical for IPU adoption.
IPUs are designed specifically for software pipelines and infrastructure tasks, making them more efficient. They can be tuned for specific requirements such as latency and throughput, and they provide a secure and isolated environment for applications.
The software in an IPU could be scalable for networking, storage, containers, or other functional aspects, depending on the needs of the clients. Cheerla mentioned IPDK (Infrastructure Programmer Programming Kit), an open-source development toolkit for IPUs that may be used to write applications for both x86 and Arm chips, such as Marvell’s Octeon. The toolkit includes functional blocks for customising and defining workloads, which may include packet processing offloading.
Intel’s ambition of developing custom processors for infrastructure providers and hyperscalers includes customer-specific IPUs. According to Intel, Xeon CPUs are used in 85 percent of datacenter infrastructure. In order to get more chips built-in its facilities, Intel has also extended its doors to non-Intel intellectual property on semiconductor platforms.
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