The die sizes and transistor counts for the AD102, AD103, and AD104 GPUs were fully disclosed by NVIDIA. In the next weeks, all three will premiere. The specifics on the flagship AD102 GPU, which is designed for the RTX 4090 graphics card, had already been published by NVIDIA, but the information on AD104 and AD103 was still lacking.
- AD102: 608 mm² die, 76.3B transistors
- AD103: 378.6 mm² die, 45.9B transistors
- AD104: 294.5 mm² die, 35.8B transistors
This means that each of the three xtor devices has a density greater than 121M per square mm (it is actually identical for AD103 and AD104). Additionally, Ampere GA102 GPU flagship has 7.5 billion fewer transistors than AD104, which has 35.8 billion transistors (28.3B). In comparison, GA102 is more than two times bigger than AD104.
The number of Render Output Units (ROP) on NVIDIA Ada GPUs is substantially more than that of the predecessor, reaching 192 ROPs for AD102. While AD104 had 80 ROPs, the AD103 GPU has the same number as GA102 (112). Rasterization performance should be enhanced by increased ROP count.
In order to make way for other logical blocks, NVIDIA removed NVLink from the design, among other adjustments.
The L2 cache, however, has grown greatly at the same period. The specific sizes for each SKU, AD102 96MB, AD103 64MB, and AD104 48MB, have now been confirmed by NVIDIA. Both RTX 4080 versions are confirmed to have fully unlocked L2 cache on their respective GPUs; the 4080 16GB has 64MB, while the 4080 12GB has 48MB.
In order to make way for other logical blocks, NVIDIA removed NVLink from the design, among other adjustments. The L2 cache, however, has grown greatly at the same period. The specific sizes for each SKU, AD102 96MB, AD103 64MB, and AD104 48MB, have now been confirmed by NVIDIA. Both RTX 4080 versions are confirmed to have fully unlocked L2 cache on their respective GPUs; the 4080 16GB has 64MB, while the 4080 12GB has 48MB.
Additionally, according to HKEPC, NVIDIA clarified what TSMC 4N—not to be confused with N4—really implies. This process is a die downsize of the TSMC 5N process, although the architecture is still 5 nm. This “clarification” only has one flaw: NVIDIA gives false information on the 4nm process.
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