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SK Hynix CEO suggests a merger between RAM and CPUs

The RAM standards, later this year, are transitioning to the DDR5 era that brings improvements and considerable performance boost compared to DDR4. However, DDR (Double Data Rate) and its faster GDDR (Graphics Double Data Rate) relative are not really that fast compared to the HBM (Hgh-Bandwidth Memory) standard, which, according to Seok-Hee Lee, Chief Executive Officer of SK Hynix, could be the foundation for the natural merger between CPUs and RAM.

At the International Reliability Physics Symposium of the IEEE (Institute of Electrical and Electronics Engineers), Lee presented his vision for a faster memory standard that would require a “convergence of memory and logic.” He presented a more gradual evolution starting with HBM:

“As the speed was increased in high-bandwidth memory by increasing the number of channels between the CPU and the memory, the speed will increase further in Processing Near Memory (PNM), where both the CPU and the memory exist within a single module. The speed will further increase in Processing In Memory (PIM), where the CPU and the memory exist within a single package. Ultimately, speed will increase further in Computing in Memory(CIM), where the CPU and the memory is integrated within a single die, to deliver high-performance computing system.”

The South Korean memory semiconductor supplier, SK Hynix, is currently the second-largest memory maker in the world, but any other type of chips like CPUs are not manufactured by the company. Thus, CEO Lee calls for a “strategic partnership” between semiconductor giants in order to form an ecosystem that can sustain the new CPU+RAM hybrids and “shape a new era, which pursues both economic and social value.”

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Lee also presented a new standard called Compute Express Link (CXL) that could complement the PCIe bus (high-speed serial computer expansion bus standard). The CXL memory has the capability of moving data faster and in a more systematic manner between CPU and graphics / compute accelerators or smart network interfaces. 

“CXL memory is being prepared as a solution that not only expands bandwidth and capacity but also realizes the value of a persistent memory, […] a solution to narrow the gap between the memory performance and the industry requirements.”

Last but not least, Lee mentioned the efforts that are being made to improve the NAND memory chips(a type of nonvolatile storage technology that does not require power to retain data) integrated into SSD storage solutions. With the jump to 10 nm nodes and below, the Icheon-based company may eventually be able to produce 600-layer NAND chips, which should greatly increase storage capacity and data transfer speeds over the current 176-layer cap.

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