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PCIe 6.0 reached its final stages of developing confirming data transfer speeds as high as 128 GB/s

If you want an irony then here’s something to think about. As we know, the latest PCIe standard in the market is the PCIe 4.0 and the next generation of PCIe memory standard is the upcoming PCIe 5.0. however, currently, we don’t have any manufacturer which has adopted the latest standard with Intel being the first to offer PCIe 5.0 capabilities with its upcoming 12th generation Alder Lake processors.

However, things are now getting interesting as earlier this week, PCI-SIG has revealed that the PCIe 6.0 specification has reached the Final Draft stages which is an important and much-needed step showing the completion of the Gen 6 PCIe technology.

The company also announced that any current SoCs conformable with version 0.9 specs can now access the new 1.0 versions. However, the only uncertainty is what applications need to upgrade and prepare for the PCIe 6.0 technology.

According to official sources, the PCIe 6. will increase the data transfer rates to 64 GT/s per pin, which is an increase from PCIe 5.0 speeds of 32 GT/s. This new technology will also remain backwards compatible with any current existing hardware while also being capable of data transfers of 128 Gb/s in all directions on the x16 interfacing.

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There are five main checkpoints that PCI Express specs have to comply with which include Concept, First Draft, Complete Draft, Final Draft, and lastly, Final. Version 0.7 of PCIe Gen 6 was the Complete Draft, appearing less than a year ago, while also allowing large corporations and major tech developers, such as Synopsys, to begin utilizing the “PCIe 6.0 controller IP and PHY in silicon.”

But the recently reached Final Draft version of PCIe 6.0 (version 0.9), is a step further as it allows for members of the PCI-SIG to review the new standards for not only patents but also for intellectual properties.

Manufacturers and developers utilizing PCIe Gen 6 version 1.0 are expected to “adopt pulse amplitude modulation with four levels (PAM-4) or signaling, which is also used for high-end networking technologies like InfiniBand as well as GDDR6X memory.” PCIe 6.0 showcases forward error correction (FEC) at minimal latencies, allowing for high rates of data while also remaining extremely efficient.

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Nivedita Bangari
Nivedita Bangari
I am a software engineer by profession and technology is my love, learning and playing with new technologies is my passion.



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