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Intel gives a brief description of the features of its upcoming Ponte Vecchio GPUs & the Sapphire Rapids-SP Xeon CPUs

At the recently held Supercomputing 2021 event, intel gave a brief session where the chip discussed its next-generation data centre roadmap and also talked about its upcoming Ponte Vecchio GPUs & the Sapphire Rapids-SP Xeon CPUs.

The company has already revealed much of the technical details regarding its next-gen data centre CPU & GPU lineup at Hot Chips 33 and at SC21, Intel re-iterated what it has already said and also revealed a few more tidbits at SuperComputing 21.

The current generation of Intel Xeon Scalable processors has been extensively adopted by our HPC ecosystem partners, and we are adding new capabilities with Sapphire Rapids – our next-generation Xeon Scalable processor that is currently sampling with customers. This next-generation platform delivers multi-capabilities for the HPC ecosystem, bringing for the first time in-package high bandwidth memory with HBM2e that leverages the Sapphire Rapids multi-tile architecture. Sapphire Rapids also brings enhanced performance, new accelerators, PCIe Gen 5, and other exciting capabilities optimized for AI, data analytics, and HPC workloads.

HPC workloads are evolving rapidly. They are becoming more diverse and specialized, requiring a mix of heterogeneous architectures. While the x86 architecture continues to be the workhorse for scalar workloads, if we are to deliver orders-of-magnitude performance gains and move beyond the exascale era, we must critically look at how HPC workloads are run within the vector, matrix, and spatial architectures, and we must ensure these architectures seamlessly work together. Intel has adopted an “entire workload” strategy, where workload-specific accelerators and graphics processing units (GPU) can seamlessly work with central processing units (CPU) from both hardware and software perspectives.

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We are deploying this strategy with our next-generation Intel Xeon Scalable processors and Intel Xe HPC GPUs (code-named “Ponte Vecchio”) that will power the 2 exaflop Aurora supercomputer at Argonne National Laboratory. Ponte Vecchio has the highest compute density per socket and per node, packing 47 tiles with our advanced packaging technologies: EMIB and Foveros. There are over 100 HPC applications running on Ponte Vecchio. We are also working with partners and customers including – ATOS, Dell, HPE, Lenovo, Inspur, Quanta, and Supermicro – to deploy Ponte Vecchio in their latest supercomputers.

Intel gives a brief description of the features of its upcoming Ponte Vecchio GPUs & the Sapphire Rapids-SP Xeon CPUs

First coming to the Sapphire Rapids-SP and the processors will be coming in two package variants, a standard, and an HBM configuration. Firstly the standard variant will be featuring a chipset design that is composed of four CXC dies featuring a die size of around 400mm2.

The four HBM2E memory packages will feature 8-Hi stacks so Intel is going for at least 16 GB of HBM2E memory per stack for a total of 64 GB across the Sapphire Rapids-SP package.

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  • Intel Sapphire Rapids-SP Xeon (Standard Package) – 4446mm2
  • Intel Sapphire Rapids-SP Xeon (HBM2E Package) – 5700mm2
  • AMD EPYC Genoa (12 CCD Package) – 5428mm2

Intel Xeon SP Families:

Family BrandingSkylake-SPCascade Lake-SP/APCooper Lake-SPIce Lake-SPSapphire RapidsEmerald RapidsGranite RapidsDiamond Rapids
Process Node14nm+14nm++14nm++10nm+Intel 7Intel 7Intel 4Intel 3?
Platform NameIntel PurleyIntel PurleyIntel Cedar IslandIntel WhitleyIntel Eagle StreamIntel Eagle StreamIntel Mountain Stream
Intel Birch Stream
Intel Mountain Stream
Intel Birch Stream
MCP (Multi-Chip Package) SKUsNoYesNoNoYesTBDTBD (Possibly Yes)TBD (Possibly Yes)
SocketLGA 3647LGA 3647LGA 4189LGA 4189LGA 4677LGA 4677LGA 4677TBD
Max Core CountUp To 28Up To 28Up To 28Up To 40Up To 56Up To 64?Up To 120?TBD
Max Thread CountUp To 56Up To 56Up To 56Up To 80Up To 112Up To 128?Up To 240?TBD
Max L3 Cache38.5 MB L338.5 MB L338.5 MB L360 MB L3105 MB L3120 MB L3?TBDTBD
Memory SupportDDR4-2666 6-ChannelDDR4-2933 6-ChannelUp To 6-Channel DDR4-3200Up To 8-Channel DDR4-3200Up To 8-Channel DDR5-4800Up To 8-Channel DDR5-5600?TBDTBD
PCIe Gen SupportPCIe 3.0 (48 Lanes)PCIe 3.0 (48 Lanes)PCIe 3.0 (48 Lanes)PCIe 4.0 (64 Lanes)PCIe 5.0 (80 lanes)PCIe 5.0PCIe 6.0?PCIe 6.0?
TDP Range140W-205W165W-205W150W-250W105-270WUp To 350WUp To 350WTBDTBD
3D Xpoint Optane DIMMN/AApache PassBarlow PassBarlow PassCrow PassCrow Pass?Donahue Pass?Donahue Pass?
CompetitionAMD EPYC Naples 14nmAMD EPYC Rome 7nmAMD EPYC Rome 7nmAMD EPYC Milan 7nm+AMD EPYC Genoa ~5nmAMD Next-Gen EPYC (Post Genoa)AMD Next-Gen EPYC (Post Genoa)AMD Next-Gen EPYC (Post Genoa)
Intel Sapphire Rapids SP Xeon HBM CPU Ponte Vecchio GPU With EMIB Forveros Packaging Technologies 4 Intel gives a brief description of the features of its upcoming Ponte Vecchio GPUs & the Sapphire Rapids-SP Xeon CPUs

Secondly, we have the Ponte Vecchio, and the chip maker outlined some key features of its flagship data centre GPU such as 128 Xe cores, 128 RT units, HBM2e memory, and a total of 8 Xe-HPC GPUs which all will be connected.

This chip will be featuring up to 408 MB of L2 cache in two separate stacks that will connect via the EMIB interconnect. This flagship from intel will also be featuring multiple dies based on Intel’s own ‘Intel 7’ process and TSMC’s N7 / N5 process nodes.

Intel also has several next-generation solutions for advanced packaging designs such as Forveros Omni and Forveros Direct as they enter the Angstrom Era of transistor development.

Next-Gen Data Center GPU Accelerators

GPU NameAMD Instinct MI200NVIDIA Hopper GH100Intel Xe HPC
Flagship ProductAMD Instinct MI250XNVIDIA H100Intel Ponte Vecchio
Packaging DesignMCM (Infinity Fabric)MCM (NVLINK)MCM (EMIB + Forveros)
GPU ArchitectureAldebaran (CDNA 2)Hopper GH100Xe-HPC
GPU Process Node6nm5nm?7nm (Intel 4)
GPU Cores14,08018,432?32,768?
GPU Clock Speed1700 MHzTBATBA
L2 / L3 Cache2 x 8 MBTBA2 x 204 MB
FP16 Compute383 TOPsTBATBA
FP32 Compute95.7 TFLOPsTBA~45 TFLOPs (A0 Silicon)
FP64 Compute47.9 TFLOPsTBATBA
Memory Capacity128 GB HBM2E128 GB HBM2E?TBA
Memory Clock3.2 GbpsTBATBA
Memory Bus8192-bit8192-bit?8192-bit
Memory Bandwidth3.2 TB/s~2.5 TB/s?5 TB/s
Form FactorDual Slot, Full Length / OAMDual Slot, Full Length / OAMOAM
CoolingPassive Cooling
Liquid Cooling
Passive Cooling
Liquid Cooling
Passive Cooling
Liquid Cooling
TDPQ4 20212H 20222022-2023?



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Nivedita Bangari
Nivedita Bangari
I am a software engineer by profession and technology is my love, learning and playing with new technologies is my passion.



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