The new AVX10 ISA (Instruction Set Architecture) from Intel has been detailed, and it includes AVX-512 compatibility for both P-Cores and E-Cores. Longhorn, a slide shared by Twitterati, reveals information about Intel’s future AVX10 ISA, which appears to come in two flavours, pre-enablement (AVX10.1) and post-enablement (AVX10.2).
Both ISAs include one notable enhancement: support for optional 512-bit FP/int, which was previously unavailable on client chips. The Intel AVX-512 ISA has been around for a long with Rocket Lake and Tiger Lake, but the firm decided to disable it in subsequent client-tier CPUs such as Alder Lake and Raptor Lake.
It appears that Intel may bring these instructions back with CPUs that implement the AVX10 ISA.
The AVX10 ISA is part of the latest APX (Advanced Performance Extensions), according to the pre and post-enablement details. It’s not as though AVX-512 has vanished completely. The instructions are still supported on the HPC side by the Xeon CPUs.
However, the client side may simply bring back AVX-512 instructions because AMD currently offers them on its Ryzen 7000 consumer CPUs, which have shown some excellent performance capabilities in specialised workloads while consuming little power. The prior AVX-512 instructions from Intel were notorious for their high power consumption.
Furthermore, the pre-enablement AVX 10.1 version only lists AVX-512 support for P-Cores, but the AVX 10.2 version also includes E-Cores. There have already been reports that Intel may bring AVX-512 back to client CPUs in some form or another in the future.
Meteor Lake is available to clients, and Granite Rapids and Sierra Forest are available to HPC subscribers. All three families have a same architecture, with the P-Cores employing Redwood Cove cores and the E-Cores employing Crestmont design. Intel has announced that their next Xeon processors, codenamed Granite Rapids, will be the first to support AVX10 and will mark the shift from AVX-512 to Intel AVX10 (no 256-bit vector extensions will be included).
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