A new AMD patent has popped up online which mentions the hybrid architecture consisting of Big and Little cores will be featured on next-gen Ryzen CPUs and APUs. There were many rumors previously which stated that AMD is going to transition to a hybrid architecture with its next-gen chips.
However, the point of the matter remains that its rival Intel has already taken a lead over AMD in a hybrid architecture. Intel will be releasing its CPU with its new architecture later this year, yes we are talking about the upcoming Alder Lake line-up.
Talking more on the Big and Little architecture, we found that it is a hybrid approach in which a CPU combines different core IPs for faster computing. This process has already been seen on the ARM chips for a while now, and AMD’s rival, Intel also quite recently, brought the technology to life on the x86 platform with its Lakefield SOC which combined Atom and Cove cores.
Intel already promised to provide a software upgrade for this upcoming hybrid architecture, however, recent sources indicate that AMD even though filling a petition, is still in the early stages of processing the technology.
The patent which was filed back in 2019 stated that AMD will transition tasks within heterogeneous processors. The existing line of AMD APUs is heterogeneous since they pack two different IPs on the same die, however, AMD plans on bringing the heterogeneous implementation to the core architecture itself.
A method, system, and apparatus determine that one or more tasks should be relocated from a first processor to a second processor by comparing performance metrics to associated thresholds or by using other indications. To relocate the one or more tasks from the first processor to the second processor, the first processor is stalled and state information from the first processor is copied to the second processor. The second processor uses the state information and then services incoming tasks instead of the first processor.
According to the patent, AMD will be connecting two core IPs to the same interconnect while they will also be internally communicating with each other, as well as sharing tasks such as core utilization, memory usage, memory access, idle/load power states, etc.
