Along with the Zen 4 cores, the AMD EPYC Genoa-X CPUs with 3D V-Cache are expected to be released this year. New information reveals the exact amount of cache and clocks that the upcoming server chips and the 2nd EPYC family with 3D V-Cache technology will have.
According to a leaked spec sheet, we can see details of two AMD EPYC Genoa-X CPUs with the same specs, but one is an ES part “100-000000892-04” and the other is a retail sample “100-000000892-06”.
Both chips support the SP5 socket and have a “B1” revision. It will have a core configuration similar to the existing Genoa chips, with 12 Zen 4 CCDs and a single I/O die, but each Zen 4 CCD will have a 3D V-cache stack with up to 64 MB of L3 cache.
That’s 384 MB of L3 cache from the CCDs, 768 MB of L3 cache from the 3D V-Cache stacks, and 96 MB of L2 cache for a total of 1248 MB cache in the AMD EPYC Genoa-X CPUs. In addition, there is 3 MB of L1 cache (instruction/data).
This is 2.6x more cache than standard Genoa chips and a 56% increase in cache amount over Milan-X. (1st Gen EPYC 3D V-Cache chips). All chips will be rated at 400W, with TDPs ranging from 320W to 400W.
The maximum clock frequency of the AMD EPYC Genoa-X chips will be 3.7 GHz, which is the same as the EPYC 9654 96-Core Genoa CPU
These chips also have a maximum thermal range of 100 degrees Celsius. We already know about four EPYC Genoa-X SKUs that were recently leaked.
The top chip will be the EPYC 9684X, which will have a maximum of 96 cores and 1152 MB of L3 cache. The EPYC 9384X will have 32 cores, the EPYC 9284X will have 24 cores, and the EPYC 9184X will have 16 cores. As with the previous generation of 3D V-Cache EPYC CPUs, all chips will be targeted at cache-optimized workloads. AMD EPYC Genoa-X CPUs are expected to be available in servers by the middle of 2023.
Also read:
![The Sleep Company [CPS] IN](data:image/svg+xml,%3Csvg%20xmlns='http://www.w3.org/2000/svg'%20viewBox='0%200%20300%20600'%3E%3C/svg%3E)
