PCI-SIG, the global body in charge of PCIe standards, has formally announced the introduction of the PCIe 6.0 specification, which supports 64 GT/s.
Features of the PCIe 6.0 Specification
- 64 GT/s raw data rate and up to 256 GB/s via x16 configuration
- Pulse Amplitude Modulation with 4 levels (PAM4) signaling and leverages existing PAM4 already available in the industry
- Lightweight Forward Error Correct (FEC) and Cyclic Redundancy Check (CRC) mitigate the bit error rate increase associated with PAM4 signaling
- Flit (flow control unit) based encoding supports PAM4 modulation and enables more than double the bandwidth gain
- Updated Packet layout used in Flit Mode to provide additional functionality and simplify processing
- Maintains backward compatibility with all previous generations of PCIe technology
This revolutionary breakthrough in PCIe technology will give two twice the power efficiency and bandwidth of the previous PCIe 5.0 specification (which only allowed for 32 GT/s), while also lowering latency and reducing bandwidth overhead. For the past two decades, PCIe has been the most important component in performance and data processing.
PCI-SIG is pleased to announce the release of the PCIe 6.0 specification less than three years after the PCIe 5.0 specification. PCIe 6.0 technology is the cost-effective and scalable interconnect solution that will continue to impact data-intensive markets like data center, artificial intelligence/machine learning, HPC, automotive, IoT, and military/aerospace, while also protecting industry investments by maintaining backward compatibility with all previous generations of PCIe technology.
— Al Yanes, PCI-SIG Chairperson and President
The PCIe 6.0 specification will serve data centers, AI and machine learning, HPC, automotive, IoT, and military aircraft, among other high data transfer markets. In data-intensive sectors, the new technology includes servers, AI/ML, networking, and storage. PCIe 6.0 uses an x16 design to allow data rates of up to 256 GB/s, resulting in low latency, decreased complexity, and little overhead bandwidth.
PAM4 (Pulse Amplitude Modulation with 4 Levels) signaling, low-latency Forward Error Correction (FEC), and Flit (Flow Control Unit)-based encoding will all be part of the new definition. As a result, the technology is both affordable and scalable. Companies will be able to future-proof their products by providing high-bandwidth, low-latency technology to consumers.
PAM4, or Pulse Amplitude Modulation with Four Levels, is a data transmission technology that uses a multilayer signal modulation scheme. Only two levels of signaling were available with the prior NRZ technology. On a serial channel, it packs two bits of information, similar to NRZ technology. Using PAM4, the PCIe 6.0 specification may provide a data rate of 64 GT/s and a bidirectional bandwidth of up to 256 GB/s in an x16 arrangement.
In PCIe 6.0 technology, the Flit, or Flow Control Unit mode, is the unit of data interchange. The Flit structure, which includes variable-sized Transaction Layer Packets (TLPs) and Data Link Layer Payloads, was adopted by the organization (DLLPs). Due to the switch to PAM4 encoding and Forward Error Correction, or FEC, which exclusively focuses on fixed-size data packets, this was a significant change.
With the PCI Express SSD market forecasted to grow at a CAGR of 40% to over 800 exabytes by 2025, PCI-SIG continues to meet the future needs of storage applications. With the storage industry transitioning to PCIe 4.0 technology and on the cusp of introducing PCIe 5.0 technology, companies will begin adopting PCIe 6.0 technology in their roadmaps to future-proof their products and take advantage of the high bandwidth and low latency that PCI Express technology offers.
— Greg Wong, Founder, and Principal Analyst, Forward Insights.
There is a growing demand for ever-increasing performance in many segments in the data center such as high-performance computing and AI. Within three to five years the application landscape will look very different and companies will likely begin updating their roadmaps accordingly. The advancement of an established standard like PCIe 6.0 architecture will serve the industry well in establishing composable infrastructure for performance-intensive computing use cases.
— Ashish Nadkarni, Group Vice President, Infrastructure Systems, Platforms and Technologies Group, IDC
For more information on PCI-SIG and PCIe 6.0 technology, visit the PCI-SIG organization’s website.
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