AMD releases the first patch of its next-generation EPYC Zen 4 CPUs for Linux bringing in new capabilities

The first enabling patches for AMD’s next-generation EPYC Zen 4 CPUs and the new capabilities built into them for Linux are now available. While AMD is still working on Zen 3 on both client and server platforms, the Linux team at AMD is already releasing the first fixes for Zen 4 support. The latest upgrades feature compatibility for AMD’s next-generation EPYC server CPUs, which will handle 12-channel memory, according to Phoronix.

AMD has previously released fixes that enable compatibility for AMD EPYC CPUs with up to 12 CCDs, so both Genoa and Bergamo are now supported by Linux. For Zen 4 CPUs, there’s also new temperature monitoring support, and the current patch adds on the memory front.

Support for up to 12-channel RAM in both RDDR5 and LDDR5 versions is now included in the new patch. The AMD EPYC Zen 4 platforms will support both RDDR5 (Registered DDR5) and LRDDR5 (Load-Reduced DDR5) memory, with LRDDR5 geared at dense memory servers. Each CPU will have up to 12 memory controllers (per socket), compared to the current 8 memory controllers per chip. According to reports, AMD’s Zen 4 processors will be labelled as “Family 19h Models 10h-1Fh and A0h-AFC.”

The EPYC Genoa chip renders revealed a total of 12 CCDs (16 cores per CCD) to reach 96 cores, while the AMD Bergamo renders also show 12 CCDs, but either Zen 4C likely has more cores per CCD or the render shown wasn’t final, as a 16 core CCD configuration would require a total of 16 Zen 4 CCDs to reach 128 cores. The final die arrangement will undoubtedly be a sight to behold.

AMD EPYC CPU Families:

Family NameAMD EPYC NaplesAMD EPYC RomeAMD EPYC MilanAMD EPYC Milan-XAMD EPYC GenoaAMD EPYC BergamoAMD EPYC Turin
Family BrandingEPYC 7001EPYC 7002EPYC 7003EPYC 7003X?EPYC 7004?EPYC 7005?EPYC 7006?
Family Launch201720192021202220222023-2024?2024-2025?
CPU ArchitectureZen 1Zen 2Zen 3Zen 3Zen 4Zen 4Zen 5
Process Node14nm GloFo7nm TSMC7nm TSMC7nm TSMC5nm TSMC5nm TSMC3nm TSMC?
Platform NameSP3SP3SP3SP3SP5SP5SP5
SocketLGA 4094LGA 4094LGA 4094LGA 4094LGA 6096LGA 6096LGA 6096
Max Core Count3264646496128256
Max Thread Count64128128128192256512
Max L3 Cache64 MB256 MB256 MB768 MB?384 MB?TBDTBD
Chiplet Design4 CCD’s (2 CCX’s per CCD)8 CCD’s (2 CCX’s per CCD) + 1 IOD8 CCD’s (1 CCX per CCD) + 1 IOD8 CCD’s with 3D V-Cache (1 CCX per CCD) + 1 IOD12 CCD’s (1 CCX per CCD) + 1 IOD12 CCD’s (1 CCX per CCD) + 1 IODTBD
Memory SupportDDR4-2666DDR4-3200DDR4-3200DDR4-3200DDR5-5200DDR5-5600?DDR5-6000?
Memory Channels8 Channel8 Channel8 Channel8 Channel12 Channel12 ChannelTBD
PCIe Gen Support64 Gen 3128 Gen 4128 Gen 4128 Gen 4128 Gen 5TBDTBD
TDP Range200W280W280W280W320W (cTDP 400W)320W (cTDP 400W)480W (cTDP 600W)

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