The first enabling patches for AMD’s next-generation EPYC Zen 4 CPUs and the new capabilities built into them for Linux are now available. While AMD is still working on Zen 3 on both client and server platforms, the Linux team at AMD is already releasing the first fixes for Zen 4 support. The latest upgrades feature compatibility for AMD’s next-generation EPYC server CPUs, which will handle 12-channel memory, according to Phoronix.
AMD has previously released fixes that enable compatibility for AMD EPYC CPUs with up to 12 CCDs, so both Genoa and Bergamo are now supported by Linux. For Zen 4 CPUs, there’s also new temperature monitoring support, and the current patch adds on the memory front.
Support for up to 12-channel RAM in both RDDR5 and LDDR5 versions is now included in the new patch. The AMD EPYC Zen 4 platforms will support both RDDR5 (Registered DDR5) and LRDDR5 (Load-Reduced DDR5) memory, with LRDDR5 geared at dense memory servers. Each CPU will have up to 12 memory controllers (per socket), compared to the current 8 memory controllers per chip. According to reports, AMD’s Zen 4 processors will be labelled as “Family 19h Models 10h-1Fh and A0h-AFC.”
The EPYC Genoa chip renders revealed a total of 12 CCDs (16 cores per CCD) to reach 96 cores, while the AMD Bergamo renders also show 12 CCDs, but either Zen 4C likely has more cores per CCD or the render shown wasn’t final, as a 16 core CCD configuration would require a total of 16 Zen 4 CCDs to reach 128 cores. The final die arrangement will undoubtedly be a sight to behold.
AMD EPYC CPU Families:
| Family Name | AMD EPYC Naples | AMD EPYC Rome | AMD EPYC Milan | AMD EPYC Milan-X | AMD EPYC Genoa | AMD EPYC Bergamo | AMD EPYC Turin |
| Family Branding | EPYC 7001 | EPYC 7002 | EPYC 7003 | EPYC 7003X? | EPYC 7004? | EPYC 7005? | EPYC 7006? |
| Family Launch | 2017 | 2019 | 2021 | 2022 | 2022 | 2023-2024? | 2024-2025? |
| CPU Architecture | Zen 1 | Zen 2 | Zen 3 | Zen 3 | Zen 4 | Zen 4 | Zen 5 |
| Process Node | 14nm GloFo | 7nm TSMC | 7nm TSMC | 7nm TSMC | 5nm TSMC | 5nm TSMC | 3nm TSMC? |
| Platform Name | SP3 | SP3 | SP3 | SP3 | SP5 | SP5 | SP5 |
| Socket | LGA 4094 | LGA 4094 | LGA 4094 | LGA 4094 | LGA 6096 | LGA 6096 | LGA 6096 |
| Max Core Count | 32 | 64 | 64 | 64 | 96 | 128 | 256 |
| Max Thread Count | 64 | 128 | 128 | 128 | 192 | 256 | 512 |
| Max L3 Cache | 64 MB | 256 MB | 256 MB | 768 MB? | 384 MB? | TBD | TBD |
| Chiplet Design | 4 CCD’s (2 CCX’s per CCD) | 8 CCD’s (2 CCX’s per CCD) + 1 IOD | 8 CCD’s (1 CCX per CCD) + 1 IOD | 8 CCD’s with 3D V-Cache (1 CCX per CCD) + 1 IOD | 12 CCD’s (1 CCX per CCD) + 1 IOD | 12 CCD’s (1 CCX per CCD) + 1 IOD | TBD |
| Memory Support | DDR4-2666 | DDR4-3200 | DDR4-3200 | DDR4-3200 | DDR5-5200 | DDR5-5600? | DDR5-6000? |
| Memory Channels | 8 Channel | 8 Channel | 8 Channel | 8 Channel | 12 Channel | 12 Channel | TBD |
| PCIe Gen Support | 64 Gen 3 | 128 Gen 4 | 128 Gen 4 | 128 Gen 4 | 128 Gen 5 | TBD | TBD |
| TDP Range | 200W | 280W | 280W | 280W | 320W (cTDP 400W) | 320W (cTDP 400W) | 480W (cTDP 600W) |
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