The yields for Taiwan Semiconductor Manufacturing Company’s (TSMC) next-generation chip manufacturing technology are outstanding. This technology, dubbed the N3e, improves TSMC’s first iteration of the N3 node, which aims to decrease some transistor dimensions to as small as 3-nanometers. Morgan Stanley, which has produced a new research study titled “Production yield of N3e is greater than predicted; reaffirm OW” and shared it on Twitter, has today’s report.
The snippet, shared by the Twitter user, states that:
N3e production yield improves; schedule being pulled in: Our recent checks with equipment vendors suggest that TSMC may freeze the N3e process flow sooner – by the end of this March. This means that volume production of N3e may start in 2Q23, around a quarter ahead of the original schedule of 3Q23.
The test production yield is much higher for N3e than N3b. Our checks suggest that the logic density of N3e is only ~8% less than that of the original N3 by cutting four EUV layers, yet it’s still 60% denser than 5nm. This makes N3e a competitive node for TSMC in terms of cost and timing.
The user Retired Engineer uploaded a study sample on the social media network Twitter. According to this extract, Morgan Stanley’s checks with equipment vendors suggest that TSMC could “lock” its design specifications for the N3E node as soon as the end of this month. This is owing to a higher-than-expected yield for the process, which means volume manufacturing, which is one of the final stages before a chip node enters mass production, may begin as early as the second quarter of next year.
Morgan Stanley’s announcement follows reports in the Taiwanese press that TSMC is having problems with its 3nm yield. The number of chips that pass quality control inspections on a single wafer is characterised as the yield of a process in the semiconductor industry. The higher the percentage, the more mature the process is. Fabs like TSMC spend their time to perfect this measure because it strengthens customer connections and increases product quality.
It also mentions the presence of an N3b node, which was previously thought to have been introduced by TSMC as a stopgap measure due to low yields. While previous reports claimed that TSMC’s customers preferred to continue with the comparatively mature 5nm node due to alleged yield issues, it’s unclear whether this is still the case.
According to TSMC’s official data for the initial N3 node released last year, the process boasts a 70 per cent higher density than the 5nm technology. Morgan Stanley’s projection of a 60% rise over 5nm and an 8% reduction over the first generation N3 is consistent with the chipmaker’s estimates.
TSMC’s chief executive officer, Dr C.C. Wei, stated at the company’s third-quarter 2021 conference call last year that the N3E node will “feature improved manufacturing process window with superior performance, power, and yield.”
The fab is now competing with Intel Corporation, a leading chipmaker in the United States, in developing the latest chip manufacturing technology. Both companies are racing to acquire new equipment and reduce transistor sizes while streamlining production and meeting market demand. Samsung Foundry, the world’s third chipmaker capable of manufacturing on the latest nodes, is supposedly looking into manufacturing process yield fraud within its ranks.
Also Read:
