Although TSMC’s comparable manufacturing processes are expected to be available before Intel’s 20A (2nm-class) and 18A (1.8nm-class) fabrication technologies, the world’s largest contract chip manufacturer believes that its N3P (3nm-class) technology will offer characteristics similar to Intel’s 18A while its N2 (2nm-class) will outperform it on all fronts in terms of power, performance, and area (PPA) advantages.
With the introduction of RibbonFET gate-all-around transistors and the backside power delivery network (BSPDN), two technologies intended to enable higher performance, lower power consumption, and increased transistor density, Intel’s 20A fabrication technology, scheduled to arrive in 2024, promises to be a breakthrough in terms of innovations. Meanwhile, Intel’s 18A production node is planned to enhance PPA already in late 2024 or early 2025 by further refining 20A’s innovations.
TSMC built its 3nm-class N3, N3E, N3P, and N3X fabrication techniques using its FinFET transistors
The largest foundry in the world’s nanosheet GAA transistors and BSPDN will be added to TSMC’s N2 node, which is scheduled to begin high-volume production in 2H 2025, while N2P, which is scheduled to begin mass production in late 2026, will introduce the latter.
In the upcoming years, one of Intel’s key objectives is to surpass TSMC in terms of technological leadership and win foundry orders from businesses in need of cutting-edge nodes. To do this, Intel plans to roll out three advanced manufacturing processes over the course of the next five quarters, and from 2H 2024 to 1H 2025, it will start mass producing its 2nm and 1.8nm-class manufacturing technologies. However, TSMC thinks that even its N3P node, which will be utilized in 2025, would provide comparable PPA to Intel’s 18A at a lower price, while its N2, even if it won’t hit the market for another year, will outperform it.
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