When Taiwan Semiconductor Manufacturing Company or TSMC first announced the development of its N2 (2 nm-class) manufacturing method in 2020, it didn’t give many details about the node or specify when it planned to start producing it. The business acknowledged this week that the technology is based on a revolutionary transistor structure, but chips using it would not be ready until 2026.
TSMC’s chief executive, C.C. Wei, revealed this week that the company’s N2 node will use gate-all-around (GAA) transistors, as planned (though he did not elaborate on details or reveal the marketing name of the architecture). The fabrication method will continue to use existing 0.33 numerical aperture extreme ultraviolet (EUV) lithography.
By the end of 2024, the technology should be ready for risk production, and by the end of 2025, it should be ready for high-volume manufacture (HVM). This suggests that the first N2-based chips will be delivered to TSMC customers in 2026.
The deployment of new process technologies at TSMC is slowing in general. TSMC has traditionally started production with a brand-new node every two years. N7 began ramping in April 2018, N5 entered HVM in April 2020, and N3 would be used for commercial production only in the second part of 2022, according to TSMC. We should expect an even longer cadence with N2, as the technology will only scale up to around the end of 2025.
The Puzzling N2 schedule of TSMC
When the business first announced N2, it simply stated that the new technology would be implemented at a brand-new facility at Baoshan, Hsinchu County, Taiwan. The site (dubbed Fab 20 by others) will house a new fab that will be completed in four phases. The project was approved by Taiwanese authorities in mid-2021, and it was then that we learnt that construction would begin in early 2022, giving us our first clues regarding TSMC’s N2 plans.
While the release date for TSMC’s N2 has been a closely guarded secret, the company has stated that it is aiming for a very mature node with predictable yield and tangible benefits over previous-generation nodes (e.g., N3 derivatives). TSMC anticipates its first Generation GAA-based node to be the best fabrication process when it ramps in the second half of 2025, despite being two or three years behind Samsung Foundry in gate-all-around transistors.
TSMC’s approach of producing a brand-new node every two years has served the company and its customers well so far. Every year, the corporation was able to deliver steady performance, power, and area increases thanks to enhanced versions (N5P, N7P, etc.) and customised variants. But, with the cadence for all-new nodes now stretching to three years, it’s unclear how the company hopes to maintain its winning run, especially as its competitors become far more active.
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