Taiwan Semiconductor Manufacturing Co. opened the 2022 TSMC Technology Symposium on Thursday, where the company traditionally announces its process technology roadmaps as well as future expansion plans.
The leading-edge nodes, which are part of TSMC’s N3 and N2 families and will be used to produce improved CPUs, GPUs, and SoCs in the next years, are one of the most important items the company revealed.
TSMC’s N2 features two important improvements as an all-new process technology platform: nanosheet transistors (also known as GAAFETs) and backside power rail, both of which promise to increase the node’s performance-per-watt characteristics. GAA nanosheet transistors contain gates on all four sides of their channels, which reduces leakage; additionally, their channels may be extended to enhance drive current and improve performance, or shortened to save power and money. TSMC’s N2 uses backside power delivery to send adequate power to these nanosheet transistors without wasting any of it, which the foundry considers being one of the most effective ways to fight back-end-of-line resistances (BEOL).
In terms of performance and power consumption, the nanosheet-based N2 node outperforms the TSMC N3E node by 10% to 15% at the same power and complexity, and by 25% to 30% at the same frequency and transistor count
However, as compared to N3E, the new node only adds around 1.1X to chip density. According to TSMC, the N2 is intended for a variety of applications, including mobile SoCs, high-performance CPUs, and GPUs. Many applications that will use N2 will also use multi-chiplet packaging to maximize performance and prices, as the world’s No. 1 foundry mentions ‘chiplet integration’ among the platform’s capabilities.
N3E, N3P, N3S, and N3X are four N3-derived manufacturing processes that will be released in the coming years. These N3 variants are projected to deliver better process windows, higher performance, larger transistor density, and increased voltages for ultra-high-performance applications. All of these technologies will enable FinFlex, a TSMC “secret sauce” feature that substantially increases design freedom and allows chip designers to precisely tune performance, power consumption, and costs.
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