Recently, PCIe Gen 4 was implemented on mainstream consumer motherboards but Synopsys is not waiting around to upgrade. Synopsys is willing to launch a complete PCI Express 6.0 solution along with the controller, PHY, and verification IP. In near future, it might not come into the hand s of consumers, but it allows for the early development and implementation of PCIe 6.0 SoC designs.
The foundation of PCIe Generation 6 is their own DesignWare IP that provides the topmost features including 64 GT/s PAM-4 signalling, FLIT mode, and L0p power state. The DesignWare Controller for PCIe 6.0 does utilize a MultiStream architecture.
The DesignWare PHY IP is able to utilize the advantage of unique and adaptive DSP algorithms. Those algorithms can optimize the digital and analogue equalization to maximize the power efficiency regardless of the channel. The ADC-based architecture is combined with the optimized datapath which allows for ultra-low latency. The senior vice president of marketing and strategy for IP at Synopsys, John Koeter has described the use and strengths of the PCIe Gen 6 specifications below:
“Advanced cloud computing, storage and machine learning applications are transferring significant amounts of data, requiring designers to incorporate the latest high-speed interfaces with minimal latency to meet the bandwidth demands of these systems. With Synopsys’ complete DesignWare IP solution for PCI Express 6.0, companies can get an early start on their PCIe 6.0-based designs and leverage Synopsys’ proven expertise. It established leadership in PCI Express to accelerate their path to silicon success.”
It will take some time before consumers have PCIe 6.0support as we have just been introduced with PCIe 4.0, and 5.0 still hasn’t made its way onto the consumer motherboards. PCIe 5.0 will come to the server platforms in 2022 with the Genoa platform of EPYC processors from AMD and Eagle Stream platform of Xeon processors from Intel.
