Samsung has officially announced the beginning of the mass production operations of its next-generation DDR5 memory which will be manufactured using the company’s 14nm EUV process node.
These new memory modules will be aimed at HPC & AI servers and are said to offer over twice the performance of DDR4 memory. Samsung also claimes that the new process node will help Samsung’s 14nm DDR5 memory to achieve an unprecedented increase in overall speeds.
In the current market, the 14nm EUV process push speeds to 7.2 Gbps which is more than twice the speed offered by DDR4 (3.2 Gbps), but, the company has plans to further expand its 14nm DDR5 memory portfolio to data centers, supercomputers, and enterprise server applications with even denser options based on 24Gb DRAM ICs. This would allow the company to scale their DDR5 memory from 512 GB – 1 TB capacities to 768 GB and 1.5 TB Dram capacities.
Last year the company had shipped the industry-first EUV DRAM in March, and the South Korean tech giant has since then increased the number of EUV layers to five to deliver today’s finest, most advanced DRAM process for its DDR5 solutions.
Samsung’s new five-layer EUV process enables the industry’s highest DRAM bit density, enhancing productivity by approximately 20%
We have led the DRAM market for nearly three decades by pioneering key patterning technology innovations,” said Jooyoung Lee, Senior Vice President and Head of DRAM Product & Technology at Samsung Electronics. “Today, Samsung is setting another technology milestone with multi-layer EUV that has enabled extreme miniaturization at 14nm — a feat not possible with the conventional argon fluoride (ArF) process. Building on this advancement, we will continue to provide the most differentiated memory solutions by fully addressing the need for greater performance and capacity in the data-driven world of 5G, AI, and the metaverse.
via Samsung
Since tapping into the five EUV layers to its 14nm DRAM, the South Korean tech giant has since then achieved the highest bit density while enhancing the overall wafer productivity by approximately 20%.
