Arm and Intel Foundry Services announced plans on Wednesday to perform design technology co-optimization (DTCO) and system technology co-optimization (STCO) on the Intel 18A fabrication technology for Arm’s mobile IP (1.8nm-class). The plan will enable Arm and IFS clients to maximise performance, reduce power consumption, and optimise die sizes in their upcoming SoCs incorporating Arm’s IP.
Under the terms of the agreement, Intel Foundry Services and Arm will co-optimize Arm’s IP and Intel’s 18A fabrication process to improve the new node’s performance, power, area, and cost advantages. The two companies will initially concentrate on mobile SoC designs, but their collaboration may eventually expand to the automotive, aerospace, data center, Internet of Things, and government applications. Arm and IFS will collaborate to create reference designs and optimised process developer kits for mobile SoCs as part of the agreement.
Chip manufacturing technologies and processor designs are extremely complex and costly in today’s world. To maximise the benefits of each new node for a specific design, foundries and chip developers now optimise transistor design, libraries, standard cells, chip layout, and interconnects, to name a few aspects of DTCO methodology.
When it comes to Intel’s 18A fabrication process, there are numerous things that can be optimised at the node and design levels to extract more PPAC benefits from the node.
One of Intel 18A’s key innovations is the use of gate-all-around (GAA) transistors known as RibbonFETs. The channels in GAA transistors are horizontally oriented and completely enclosed by gates.
These GAA channels are formed via epitaxy and selective material removal, allowing designers to fine-tune them by varying the width of the transistor channels to achieve higher performance or lower power consumption. If everything goes well, they will be able to reduce transistor leakage current and performance variability, which will open up new opportunities for DTCO.
Another advantage of the 18A process is its PowerVia backside power delivery network (PDN). The PDN must be customised for a specific design and process technology in order to efficiently provide power and respond quickly to the behaviour of a modern processor, which can vary significantly depending on the workload.
Client and smartphone SoCs should be optimised for burst behaviour, whereas data center SoCs should be optimised for constant high loads — which is why Intel and Arm will only address smartphone SoCs for the time being.
One thing to keep in mind about Intel’s 18A process technology is that it will be used to make chips at various IFS locations around the world. As fabless chip designers seek to localise chip production, this will be an advantage of this fabrication process.
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