CoreScore recorded new recorded featuring the densest arrangement of RISC-V cores

CoreScore benchmark has recorded a new world record featuring the densest arrangement of RISC-V cores which has been achieved by pairing 6,000 RISC-V SERV cores and one of Xilinx’s most powerful FPGA designs, the VCU128 board.

This benchmark is simulated to check how many SERV cores can be deployed on a single piece of silicon, and the Xilinx’s Virtex UltraScale+ VCU128 FPGA is capable of fitting as many as 6,000 SERV cores via its internal reconfiguration. The previous record-holder had a total of 5,087 cores hosted on Xilinx’s VCU118.

“What do you do when you have the award-winning SERV, the world’s smallest RISC-V CPU? Well, among other things, we, of course, want to see how many SERV cores you can fit into various devices. This is what CoreScore is for. And on top of that list of currently 30 boards, we can now find Sylvain Lefebvre and his Xilinx VCU128 board that fits 6000 SERV cores.”

However, one thing to note here is that the cores used are not the typical cores that you’d find on your best CPUs for gaming from Intel or AMD, instead, they are stripped-down, barebones bit-serial work units that include as few extraneous functions as possible.

Using this approach we can minimize the total die space occupied by each core and the design can achieve performance via workload parallelization, not from the obvious processing grunt from each core.

“We are nearing the max with 98.5% LUTs [Lookup Tables] (and 100% BRAM [Block RAM]) of the VCU128 FPGA utilized. It’s been great fun working with Olof Kindgren on this, and it was a perfect intro to our Xilinx VCU128 monster.”

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