AMD has released a set of patches for the company’s EDAC (Error Detection and Correction) driver code for the Zen 4 microarchitecture-based next-generation EPYC processors. According to the new patches, the upcoming CPUs will support unprecedented memory bandwidth and capacity per socket.
The patches (discovered by Phoronix) add DDR5 registered DIMMs (RDIMMs) and DDR5 load-reduced DIMMs (LRDIMMs) support for the fourth-generation EPYC processors codenamed Genoa (Family 19h Models 10h-1Fh and A0h-AFC CPUs).
The patches also confirm that the upcoming EPYC 7004-series server parts will support up to 12 memory controllers per socket, up from AMD’s current server parts’ eight. We do not yet know how many DIMMs per channel (DPC) the chips will support.
Twelve 64-bit DDR5 memory channels would theoretically increase the memory bandwidth available to Genoa processors to a whopping 460.8 GB/s per socket, a significant increase over the current-generation EPYC CPUs DDR4-3200 memory bandwidth of 204.8 GB/s.
Memory bandwidth will not be the only improvement on EPYC ‘Genoa’ CPUs in the next generation. Twelve memory channels will also allow the new processors to have larger memory capacities. Samsung has already demonstrated 512GB DDR5 RDIMMs and confirmed the possibility of 768GB DDR5 RDIMMs. AMD’s next-generation server processors could support up to 6TB of memory even with 12 512GB modules (up from 4TB today).
If Genoa supports two RDIMMs per channel, that capacity can be increased to 12TB of DDR5. With LRDIMMs (due to octal-ranked module architecture), AMD could increase capacity per memory channel and per socket even further, albeit at the expense of performance.
AMD’s EPYC 7004-series ‘Genoa’ processors will provide noticeable memory improvements over existing server processors, resulting in improved real-world performance.
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