AMD (NASDAQ: AMD) has officially announced the launch of the Versal Premium Series Gen 2, an advanced adaptive System-on-Chip (SoC) platform designed to deliver unparalleled system acceleration across a variety of demanding workloads. This groundbreaking series will be the first in the FPGA industry to feature Compute Express Link (CXL®) 3.1 and PCIe® Gen6, along with support for LPDDR5X memory in hard IP.
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AMD launches Versal Premium Series Gen 2 adaptive SoCs
Revolutionizing Data Processing
Introducing these next-generation interface and memory technologies marks a significant leap forward in how data is accessed and transferred between processors and accelerators. With CXL 3.1 and LPDDR5X, the Versal Premium Series Gen 2 is poised to meet the increasing demands for real-time processing and storage in data-intensive applications across various sectors, including data centers, communications, test and measurement, and aerospace and defense.
Salil Raje, Senior Vice President and General Manager of the Adaptive and Embedded Computing Group at AMD, stated, “System architects are constantly looking to pack more data into smaller spaces and move data more efficiently between parts of the system. Our latest addition to the Versal Gen 2 portfolio helps customers improve overall system throughput and utilization of memory resources to achieve the highest performance and unlock insights for their most demanding applications from the cloud to the edge.”
Accelerating Host Connectivity
AMD is committed to open innovation, exemplified by its support for CXL, an open industry-standard interconnect that enhances connectivity between processors and devices like FPGA-based accelerators. The Versal Premium Gen 2 devices, equipped with CXL 3.1 and PCIe Gen6, provide industry-leading, high-bandwidth host CPU-to-accelerator connectivity.
- PCIe Gen6 offers a 2-4X faster line rate compared to competing FPGAs that support PCIe Gen4 or Gen5.
- CXL 3.1, running on PCIe Gen6, delivers double the bandwidth of competing devices with CXL 2.1, all while maintaining similar latencies and enhanced fabric and coherency capabilities.
By integrating the Versal Premium Series Gen 2 with AMD EPYC™ CPUs, system architects can leverage the latest FPGA technology to accelerate data-intensive applications, effectively addressing the rapid growth of data demands. The CXL interface also introduces memory coherency, enabling true heterogeneous, accelerated computing.
Boosting Memory Bandwidth and Utilization
The Versal Premium Series Gen 2 adaptive SoCs are engineered to enhance memory bandwidth, facilitating faster data transfers and real-time responsiveness. With LPDDR5X memory connectivity reaching speeds of up to 8533 Mb/s, this ultra-fast memory technology enables up to 2.7X faster host connectivity compared to devices using LPDDR4/5 memory.
Moreover, connectivity to CXL memory expansion modules allows for 2.7X more total bandwidth than LPDDR5X memory alone. This capability enables scalable memory pooling and extension for multiple accelerators, optimizing memory utilization and increasing both bandwidth and capacity. By dynamically allocating a memory pool for multiple devices, the Versal Premium Series Gen 2 is designed to enhance memory utilization in a Multi-Headed Single Logic Device (MH-SLD) configuration, operating efficiently without the need for a fabric or switch while supporting up to two CXL hosts.
Enhancing Data Security
Security is paramount in today’s data-driven world, and the Versal Premium Series Gen 2 addresses this need with enhanced features that ensure data is transferred quickly and securely, both in transit and at rest. It is the industry’s first FPGA device to support integrated PCIe® Integrity and Data Encryption (IDE) in hard IP.
- Inline encryption built into hard DDR memory controllers secures data at rest.
- 400G High-Speed Crypto Engines enable the device to secure user data at up to 2X faster line rates, facilitating quicker secure data transactions.
Looking Ahead
AMD plans to release development tools for the Versal Premium Series Gen 2 in Q2 2025, with silicon samples expected to be available by early 2026. Production shipments are anticipated to begin in the second half of 2026.
