Scientists and engineers have been reducing transistors for decades, to the point where their tiniest characteristics are merely tens of atoms. Moore’s Law, which projected that the density of active components in integrated chips would double every two years, has guided the rate of advancement in miniaturising transistors from the first integrated circuits in the 1950s.

Progress in this direction has slowed dramatically in recent years, as we all know. The fundamental reason for this is that we are rapidly reaching the physical boundaries of what is achievable with currently available materials and modern production technologies.

We can’t create transistor gates, which control the flow of current from the source to the drain, any smaller than 5 nm due to a phenomenon known as quantum tunnelling, which prohibits them from working properly. Because of their physical qualities, materials like graphene and carbon nanotubes may be crucial in shrinking transistors even more, but getting from there to manufacturing functioning devices will take time.

Chinese researchers claim to have constructed the lowest gate length transistor ever documented in a paper published this week. This achievement was made feasible by combining graphene and molybdenum disulfide and stacking them into a two-step staircase structure.

The source is located on the upper step, while the drain is located on the bottom step. Both are built of a titanium palladium alloy, with the surface of the stairs being formed of a single sheet of a semiconductor material called molybdenum disulfide, which is sitting on a layer of electrical insulator hafnium dioxide.

The interior of the higher level is a real sandwich of aluminium covered in aluminium oxide that sits on top of a single layer of carbon atoms called graphene. Except for a small gap in the vertical wall of the higher stage, where the graphene sheet is allowed to contact the molybdenum disulfide, the aluminium oxide acts as an electrical insulator. A thick coating of silicon dioxide supports the entire staircase structure.

Transistor — Image credit: Chakrabartty Lab

The key to this design is that it uses the graphene sheet’s edge, which means that when the gate is turned on, it’s only 0.34 nm wide—roughly the same as the graphene layer itself. The fact that this “side-wall transistor” has little current leakage due to greater off-state resistance is also noteworthy. This characteristic could be used by manufacturers in low-power applications. Best of all, it would be relatively simple to construct, despite the fact that several of the prototypes required a significant amount of voltage to operate.

Tian-Ling Ren, a researcher from Tsinghua University, co-authored the study and speculated that this could be “the last node for Moore’s law.” He also feels that shrinking the gate size to less than 0.34 nm is nearly difficult.

Of course, the researchers behind the new transistor simply demonstrated that a functional transistor could be created with one-atom thin materials without devising a new process for precision layer placement. Building billions of these side-wall transistors in a reliable manner is still a long way off, but it is an important step in the right direction, fueling hopes for quicker, more power-efficient devices in the future.

Meanwhile, Samsung, Intel, and TSMC are working hard to bring gate-all-around (GAA-FET) transistors to market and standardise chiplet interconnects.