TSMC has shared the latest information about the company’s leading-edge manufacturing nodes. Dr. Yuh Jier Mii, TSMC’s senior vice president of research and development, has shared the info about the latest semiconductor manufacturing processes of fab, as well as its N3, N4, N5, and N6 process nodes.
Dr. Mii highlighted TSMC’s increased research and development spending and headcount to stand at record levels. He stated that since the fab brought the 7nm process in 2018, it has successfully shipped more than one billion chips manufactured by it.
Coming to the 6nm process node of TSMC, Dr. Mii said, this process improves logic density by 18% over the N7 process and uses more layers with supreme ultraviolet lithography at the time of the production process. Fewer masks usage hints that TSMC might increase EUV adoption with the latest process, and the executive also said that N4 risk production will begin in the third quarter of 2021.
Dr. Mii said that comparing to the N5, the N3 process has seen more than twice the tape-outs in its first year. In the semiconductor industry, a tape-out refers to chip designers finalizing their designs before sending them over to a fab.
Dr. Mii has highlighted that nanosheet transistors were able to implement tighter threshold voltage control. According to the executive, the nanosheet transistors have managed to “demonstrate nanosheet transistors with more than 15% lower Vt variations as shown in blue compared to that of a very good FinFET transistor as shown in red.“
Earlier this year, Dr. Mark Liu, the chairman of TSMC focused on the carbon nanotube transistors at the ISSC 2021 conference, where he pointed out new material development as a key breakthrough in the area.
