Samsung announced on Thursday that its 3GAE (3 nm-class gate-all-around early) fabrication method is on pace to begin high-volume production this quarter (i.e., in the coming weeks). Not only is this the first 3nm-class manufacturing method in the industry, but it’s also the first node to incorporate gate-all-around field-effect transistors (GAAFETs).
The 3GAE process technology from Samsung Foundry is the company’s first to use GAA transistors, which Samsung refers to as multi-bridge channel field-effect transistors (MOSFETs).
The business made a lot of claims while describing their 256Mb GAAFET SRAM chip developed with its 3GAE technology. Samsung claims that the technique will result in a 30% performance boost, a 50% reduction in power usage, and up to an 80% increase in transistor density (including a mix of logic and SRAM transistors). However, it remains to be seen how Samsung’s actual mix of performance and power usage would play out.
About three years ago, Samsung unveiled its 3GAE and 3GAP nodes
When compared to currently employed FinFETs, GAAFETs have a lot of advantages in principle. Channels in GAA transistors are horizontal and flanked by gates. The GAA channels are created using epitaxy and selective materials removal, allowing designers to fine-tune them by changing the transistor channel width. Wider channels provide a better performance, while narrower channels provide lower power.
Such precision reduces transistor leakage current (i.e., lowers power consumption) and transistor performance variability (provided everything works correctly), resulting in shorter time-to-yield, shorter time-to-market, and higher yields. According to a recent presentation by Applied Materials, GAAFETs have the potential to reduce cell space by 20% to 30%.
Applied recently announced high-vacuum IMS (Integrated Materials Solution) technologies to address a major problem in GAA transistor manufacturing: depositing multi-layer gate oxide and metal gate stacks across the channels in the limited space provided. Applied Materials’ first new IMS technique uses integrated atomic layer deposition (ALD), heating, plasma treatment, and metrology stages to manufacture gate oxide that is 1.5 angstroms thinner. Dipole engineering and some ALD stages are combined in the metal gate IMS.
As an ‘early’ 3nm-class manufacturing technology, Samsung’s 3GAE will be employed primarily by Samsung LSI (Samsung’s chip development arm) and possibly one or two of SF’s other alpha customers.
Expect 3GAE technology will be widely employed, assuming that yields and performance of those products fulfil expectations, given that Samsung’s LSI and other early consumers of SF prefer to create chips in very high volumes.