IN recent news we have the details of the AMD’s next-generation EPYC Turin CPUs based on the Zen 5 architecture surfacing online and they are revealed by ExecutableFix & Greymon55. The details talked about the next-gen EPYC TDPs & core counts which we can expect from the first server chips powered by the new Zen architecture.
As we already know, AMD’s 5th Gen EPYC family has codenamed Turin, and it will replace the Genoa lineup however it will also be reportedly compatible with the SP5 platform. And also the Turin line of chips could utilize package designs unlike we have ever seen before.
There are reports that Turin CPUs will be an evolution of the stacked 3D Chiplet designs which we will see in the coming EPYC Milan-X CPUs later this year. Looking at the development of the Turin and also that it will hit the market years later, we can theorize that these EPYC chips will have multiple CCD & Cache stacks on top of the base die.
AMD’s Genoa CPUs are rumored to feature up to 96 cores & Bergamo which is the evolution to Genoa on the same Zen 4 architecture will be featuring a higher core count of 128 cores. But with the case of Turin, it is being rumored that we could very likely see PCIe Gen 6.0 interface and up to 256 cores on a single chip however if AMD is going for stacked X3D chiplets then the core count may increase.
We have seen many previous rumors where a brand new package layout was stated to feature up to 16 CCDs on the SP5 socket. As for the TDP’s it is reported that EPYC Turin will have a max configurable TDP of up to 600W. The upcoming EPYC Genoa CPUs with 96 cores are going to feature cards of up to 400W and the SP5 socket will reportedly have a peak power draw of up to 700W.
AMD EPYC CPU Families:
|Family Name||AMD EPYC Naples||AMD EPYC Rome||AMD EPYC Milan||AMD EPYC Milan-X||AMD EPYC Genoa||AMD EPYC Bergamo||AMD EPYC Turin|
|Family Branding||EPYC 7001||EPYC 7002||EPYC 7003||EPYC 7003X?||EPYC 7004?||EPYC 7005?||EPYC 7006?|
|CPU Architecture||Zen 1||Zen 2||Zen 3||Zen 3||Zen 4||Zen 4||Zen 5|
|Process Node||14nm GloFo||7nm TSMC||7nm TSMC||7nm TSMC||5nm TSMC||5nm TSMC||3nm TSMC?|
|Socket||LGA 4094||LGA 4094||LGA 4094||LGA 4094||LGA 6096||LGA 6096||LGA 6096|
|Max Core Count||32||64||64||64||96||128||256|
|Max Thread Count||64||128||128||128||192||256||512|
|Max L3 Cache||64 MB||256 MB||256 MB||768 MB?||384 MB?||TBD||TBD|
|Chiplet Design||4 CCD’s (2 CCX’s per CCD)||8 CCD’s (2 CCX’s per CCD) + 1 IOD||8 CCD’s (1 CCX per CCD) + 1 IOD||8 CCD’s with 3D V-Cache (1 CCX per CCD) + 1 IOD||12 CCD’s (1 CCX per CCD) + 1 IOD||12 CCD’s (1 CCX per CCD) + 1 IOD||TBD|
|Memory Channels||8 Channel||8 Channel||8 Channel||8 Channel||12 Channel||12 Channel||TBD|
|PCIe Gen Support||64 Gen 3||128 Gen 4||128 Gen 4||128 Gen 4||128 Gen 5||TBD||TBD|
|TDP Range||200W||280W||280W||280W||320W (cTDP 400W)||320W (cTDP 400W)||480W (cTDP 600W)|