Wednesday, December 8, 2021

AMD’s next-gen EPYC Turin CPUs to feature max 600W TDPs

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IN recent news we have the details of the AMD’s next-generation EPYC Turin CPUs based on the Zen 5 architecture surfacing online and they are revealed by ExecutableFix & Greymon55. The details talked about the next-gen EPYC TDPs & core counts which we can expect from the first server chips powered by the new Zen architecture.

As we already know, AMD’s 5th Gen EPYC family has codenamed Turin, and it will replace the Genoa lineup however it will also be reportedly compatible with the SP5 platform. And also the Turin line of chips could utilize package designs unlike we have ever seen before.

There are reports that Turin CPUs will be an evolution of the stacked 3D Chiplet designs which we will see in the coming EPYC Milan-X CPUs later this year. Looking at the development of the Turin and also that it will hit the market years later, we can theorize that these EPYC chips will have multiple CCD & Cache stacks on top of the base die.

AMD’s Genoa CPUs are rumored to feature up to 96 cores & Bergamo which is the evolution to Genoa on the same Zen 4 architecture will be featuring a higher core count of 128 cores. But with the case of Turin, it is being rumored that we could very likely see PCIe Gen 6.0 interface and up to 256 cores on a single chip however if AMD is going for stacked X3D chiplets then the core count may increase.

We have seen many previous rumors where a brand new package layout was stated to feature up to 16 CCDs on the SP5 socket. As for the TDP’s it is reported that EPYC Turin will have a max configurable TDP of up to 600W. The upcoming EPYC Genoa CPUs with 96 cores are going to feature cards of up to 400W and the SP5 socket will reportedly have a peak power draw of up to 700W.

AMD EPYC CPU Families:

Family BrandingEPYC 7001EPYC 7002EPYC 7003EPYC 7003X?EPYC 7004?EPYC 7005?EPYC 7006?
Family Launch201720192021202220222023-2024?2024-2025?
CPU ArchitectureZen 1Zen 2Zen 3Zen 3Zen 4Zen 4Zen 5
Process Node14nm GloFo7nm TSMC7nm TSMC7nm TSMC5nm TSMC5nm TSMC3nm TSMC?
Platform NameSP3SP3SP3SP3SP5SP5SP5
SocketLGA 4094LGA 4094LGA 4094LGA 4094LGA 6096LGA 6096LGA 6096
Max Core Count3264646496128256
Max Thread Count64128128128192256512
Max L3 Cache64 MB256 MB256 MB768 MB?384 MB?TBDTBD
Chiplet Design4 CCD’s (2 CCX’s per CCD)8 CCD’s (2 CCX’s per CCD) + 1 IOD8 CCD’s (1 CCX per CCD) + 1 IOD8 CCD’s with 3D V-Cache (1 CCX per CCD) + 1 IOD12 CCD’s (1 CCX per CCD) + 1 IOD12 CCD’s (1 CCX per CCD) + 1 IODTBD
Memory SupportDDR4-2666DDR4-3200DDR4-3200DDR4-3200DDR5-5200DDR5-5600?DDR5-6000?
Memory Channels8 Channel8 Channel8 Channel8 Channel12 Channel12 ChannelTBD
PCIe Gen Support64 Gen 3128 Gen 4128 Gen 4128 Gen 4128 Gen 5TBDTBD
TDP Range200W280W280W280W320W (cTDP 400W)320W (cTDP 400W)480W (cTDP 600W)


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Avatar of Nivedita Bangari
Nivedita Bangari
I am a software engineer by profession and technology is my love, learning and playing with new technologies is my passion.


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