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Intel releases official details about its Sapphire Rapids-SP Xeon CPUs

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The official details are in and we now have the information about Intel’s next-generation Sapphire Rapids-SP CPU lineup. This lineup will be a part of the 4th Generation of the Xeon Scalable family.

According to the information released by Intel, the next-generation Sapphire Rapids-SP CPU lineup will consist of a range of new technologies with the most important being the seamless integration of multiple chiplets or ‘Tiles’.

The lineup will replace the Ice Lake-SP family and will go all on board with the ‘Intel 7’ process node. Sapphire Rapids will also be featuring the performance-optimized Golden Cove core architecture that delivers a 20% IPC improvement over Willow Cove core architecture.

For this next-generation server processor, Intel has used a quad multi-tile chiplet design coming in HBM and non-HBM flavours. The chip acts as one singular SOC and each thread has full access to all resources on all tiles. This provides low latency and high cross-section bandwidth across the entire SOC. Each tile is further composed of three main IP blocks & which are detailed below:

Compute IP

  • Cores
  • Acceleration Engines

I/O IP

  • CXL 1.1
  • PCIe Gen 5
  • UPI 2.0
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Memory IP

  • DDR5
  • Optane
  • HBM

the key changes which the Sapphire Rapids will bring to the data centre platform include AMX, AiA, FP16, and CLDEMOTE capabilities. The Accelerator Engines is promised to increase the effectiveness of each core by offloading common-mode tasks. This will increase performance & decrease the time taken to achieve the necessary task.

Coming to the I/O advancements, Intel has introduced CXL 1.1 to offers accelerator and memory expansion in the data centre segment. There’s also an improved multi-socket scaling via Intel UPI that delivers up to 4 x24 UPI links at 16 GT/s and a new 8S-4UPI performance-optimized topology. This new tile architecture design boosts the cache beyond 100 MB along with Optane Persistent Memory 300 series support.

Intel also announced that its Sapphire Rapids-SP CPUs can house up to four HBM packages, all offering significantly higher DRAM bandwidth than a baseline Sapphire Rapids-SP Xeon CPU with 8-channel DDR5 memory. The support for HBM memory will offer both increased capacity and bandwidth.

Intel Sapphire Rapids-SP Xeon CPU Platform

coming to the Sapphire Rapids-SP Xeon lineup, this will make use of 8 channel DDR5 memory offering speeds of up to 4800 Mbps & support PCIe Gen 5.0 on the Eagle Stream platform. This will introduce the LGA 4677 socket replacing the LGA 4189 socket for the upcoming Cedar Island & Whitley platform housing the Cooper Lake-SP and Ice Lake-SP processors, respectively.

The top-end unit of the lineup will feature 56 cores with a TDP of 350W and will be a low-bin split variant meaning that it will be using a tile or MCM design. The Sapphire Rapids-SP Xeon CPU will be composed of a 4-tile layout with each tile featuring 14 cores each.

Following are the leaked configurations:

  • Sapphire Rapids-SP 24 Core / 48 Thread / 45.0 MB / 225W
  • Sapphire Rapids-SP 28 Core / 56 Thread / 52.5 MB / 250W
  • Sapphire Rapids-SP 40 Core / 48 Thread / 75.0 MB / 300W
  • Sapphire Rapids-SP 44 Core / 88 Thread / 82.5 MB / 270W
  • Sapphire Rapids-SP 48 Core / 96 Thread / 90.0 MB / 350W
  • Sapphire Rapids-SP 56 Core / 112 Thread / 105 MB / 350W

The Intel Saphhire Rapids CPUs will contain 4 HBM2 stacks with a maximum memory of 64 GB (16GB each). The company will be launching their Sapphire Rapids most probably in 2022 followed by HBM variants that are expected to launch around 2023.

​Intel Xeon SP Families:

Family BrandingSkylake-SPCascade Lake-SP/APCooper Lake-SPIce Lake-SPSapphire RapidsEmerald RapidsGranite RapidsDiamond Rapids
Process Node14nm+14nm++14nm++10nm+Intel 7Intel 7Intel 4Intel 3?
Platform NameIntel PurleyIntel PurleyIntel Cedar IslandIntel WhitleyIntel Eagle StreamIntel Eagle StreamIntel Mountain Stream
Intel Birch Stream
Intel Mountain Stream
Intel Birch Stream
MCP (Multi-Chip Package) SKUsNoYesNoNoYesTBDTBD (Possibly Yes)TBD (Possibly Yes)
SocketLGA 3647LGA 3647LGA 4189LGA 4189LGA 4677LGA 4677LGA 4677TBD
Max Core CountUp To 28Up To 28Up To 28Up To 40Up To 56TBDUp To 120?TBD
Max Thread CountUp To 56Up To 56Up To 56Up To 80Up To 112TBDUp To 240?TBD
Max L3 Cache38.5 MB L338.5 MB L338.5 MB L360 MB L3105 MB L3TBDTBDTBD
Memory SupportDDR4-2666 6-ChannelDDR4-2933 6-ChannelUp To 6-Channel DDR4-3200Up To 8-Channel DDR4-3200Up To 8-Channel DDR5-4800Up To 8-Channel DDR5-5200?TBDTBD
PCIe Gen SupportPCIe 3.0 (48 Lanes)PCIe 3.0 (48 Lanes)PCIe 3.0 (48 Lanes)PCIe 4.0 (64 Lanes)PCIe 5.0 (80 lanes)PCIe 5.0PCIe 6.0?PCIe 6.0?
TDP Range140W-205W165W-205W150W-250W105-270WUp To 350WTBDTBDTBD
3D Xpoint Optane DIMMN/AApache PassBarlow PassBarlow PassCrow PassCrow Pass?Donahue Pass?Donahue Pass?
CompetitionAMD EPYC Naples 14nmAMD EPYC Rome 7nmAMD EPYC Rome 7nmAMD EPYC Milan 7nm+AMD EPYC Genoa ~5nmAMD Next-Gen EPYC (Post Genoa)AMD Next-Gen EPYC (Post Genoa)AMD Next-Gen EPYC (Post Genoa)
Launch201720182020202120222023?2024?2025?

source

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Avatar of Nivedita Bangari
Nivedita Bangari
I am a software engineer by profession and technology is my love, learning and playing with new technologies is my passion.

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