AMD earlier announced that they are working on new technology for their Ryzen CPUs. The technology is called the 3D V-Cache technology which takes up to 64 megabytes of additional L3 cache & stacks it on top of Ryzen CPUs.
It’s known that the modern AMD Zen 3 CPUs have in their design the accessibility to allow for the 3D cache to be stacked from the beginning. This small detail proves that Advanced Micro Devices (AMD) has been secretly working on this new technology for several years now.
However, now finally we have more details about this new technology which AMD has been working for a long time. Yuzo Fukuzaki from the website TechInsights has provided more details about this new advancement in cache memory for AMD and Fukuzaki has found some connection points on the Ryzen 9 5950X.
The report further explains that the stacking installation process utilizes a technology called “through-silicon” vias, or TSV. It will attach the second layer of the SRAM to the Ryzen 5000 chip through hybrid bonding. Then the company will be using copper for the TSV instead to allow for more thermal efficiency and more bandwidth.
He also notes in his LinkedIn article about the subject
To cope with the #memory_wall problem, cache memory design is matters. Please take the chart in the image attached, Cache density trend over process nodes. In the best timing for economical reasons, 3D memory integration on Logic can contribute to having higher performance. See #IBM #Power chips have a huge amount of cache and strong trend. They can do it because of the high-end server CPU. With #Chiplet CPU integration started by AMD, they can use #KGD (Known Good Die) to get rid of low yield concerns with monolithic large scale die. This innovation has been expected at 2022 in #IRDS (International Roadmap Devices and Systems) More Moore and AMD will do it.
Diving, even more, deeper into how the 3d V-Cache connects, the folks at TechInsights have even worked their way through the technology in reverse while providing some additional results of what was found. This is the result:
- TSV pitch; 17μm
- KOZ size ; 6.2 x 5.3 μm
- TSV counts rough estimation; about 23 thousand!!
- TSV process position; Between M10-M11 (15 Metals in total, starting from M0)
For now, it’s only wishful thinking that AMD will be implementing the 3D V-Cache with its future structures, such as the Zen 4 architecture. For more information stay tuned.
