For Taiwan Semiconductor Manufacturing Company (TSMC), being the world’s largest foundry with nearly 500 customers has its peculiarities. On the one hand, the chipmaker can cater to almost any client with almost any requirements. On the other hand, it has to stay ahead of everyone else both in terms of technology and in terms of capacity.
As far as capacity is concerned, TSMC is in no range to be challenged by any competitor for years. As for fabrication technologies, the Taiwanese chipmaker has recently reiterated that it’s confident that its 2nm, 3nm, and 4nm processes will be available on time and will be more advanced than competing nodes.
Earlier this year, TSMC significantly boosted its Capital Expenditure budget of 2021 to a $25 – $28 billion range, and further increased it to around $30 billion as a part of its three-year plan to spend $100 billion on manufacturing capacities and research and development.
Keeping the global chip shortage in mind, about 80% of TSMC’s $30 billion capital budget this year will be spent on expanding capacities for advanced technologies, such as 3nm, 4nm/5nm, and 6nm/7nm. Analysts from China Renaissance Securities believe that by the end of the year, most of the money on advanced nodes will be used to expand the company’s 5nm capacity to 110,000 ~ 120,000 wafer starts per month (WSPM). Meanwhile, TSMC stated that 10% of its capital expenditure will be allocated for mask making and advanced packaging, whereas another 10% will be spent on specialty technologies (which includes tailored versions of mature nodes).
TMSC’s most recent capital expenditure hike to $30 billion was made after Intel announced its IDM 2.0 strategy (that involves in-house production, outsourcing, and foundry operations) and to a large degree gives an assurance about TMSC’s confidence in both short-term and long-term future even ahead of intensified competition.
“As a leading pure-play foundry, TSMC has never been short on competition in our 30-plus-year history, yet we know how to compete,” said C.C. Wei, president, and CEO of TSMC, at a recent conference call with analysts and investors, according to Anand Tech. “We will continue to focus on delivering technology leadership, manufacturing excellence, and earning our customers’ trust. The last point, customers’ trust, is fairly important because we do not have internal products that compete with customer.”
5nm Gaining Customers
In mid-2020, TSMC was the first company to start high volume manufacturing (HVM) of chips using its 5nm process technology.
Initially, the node was used solely for the company’s top customers — Apple and HiSilicon. HiSilicon’s shipments stopped on September 14, which left all of the leading-edge capacity to Apple. By now, more customers are ready with their 5nm designs, so the adoption of this node is growing. Meanwhile, TSMC says, compared to its expectations just several months ago, more customers are planning to use the 5nm family of technologies (including N5, N5P, and N4).
“N5 is already in its second year of volume production with yield better than our original plan,” said Mr. Wei. N5 demand continues to be strong, driven by smartphone and HPC applications, and we expect N5 to contribute around 20% of our wafer revenue in 2021. […] In fact, we are seeing stronger engagement with more customers on 5 nm and 3 nm [versus 7 nm at similar stages]. The engagement is so strong that we have to really prepare the capacity for it.”
Analysts from China Renaissance estimate that TSMC’s 5nm features a transistor density of around 170 million transistors per square millimeter (MTr/mm2), which if accurate, makes it the densest technology available today. By contrast, “Samsung’s Foundry’s 5LPE can boast with about 125 MTr/mm2 ~130 MTr/mm2, whereas Intel’s 10 nm features an approximately 100 MTr/mm2 density.”
In the coming weeks, TSMC is set to start making chips using a performance-enhanced version of its 5nm technology that will increase frequencies by up to 5% or reduce power consumption by up to 10% (at the same complexity). This tech is called the N5P
4nm: On Track for Next Year
TSMC’s N5 family of technologies also includes the evolutionary 4nm process that will enter risk production later this year and will be used for mass production in 2022.
This technology will keep the same design infrastructure, IPs, SPICE simulation programs, and is set to provide further PPA (power, performance, area) advantages over N5. Meanwhile, since 4nm further extends the usage of EUV lithography tools, it also reduces mask counts, process steps, risks, and costs.
“N4 will leverage the strong foundation of N5 to further extend our 5 nm family,” said Mr. Wei. “N4 is a straightforward migration from N5 with compatible design rules while providing further performance, power, and density enhancement for the next wave of 5-nanometer products. N4 risk production is targeted for the second half this year and volume production in 2022.”
3nm: Due in H2 2022
In 2022, TSMC will launch its brand-new 3nm manufacturing process, which will keep using FinFET transistors but is expected to offer the whole package of PPA improvements.
TSMC’s 3nm promises to reduce power consumption by 25% – 30% (at the same performance and complexity) or increase performance by 10% – 15% (at the same power and complexity), compared to the 5nm process. All the while the new node will also improve transistor density by 1.1 to 1.7 times depending on the structures (1.1X for analog, 1.2X for SRAM, 1.7X for logic).
3nm will further increase the number of EUV layers but will keep using DUV lithography. Also, since the technology keeps using FinFET, it will not require a new generation of EDA (electronic design automation) tools redesigned from scratch and development of all-new IPs, which might become a competitive advantage over Samsung Foundry’s Gate-All-Around FETs (GAAFETs)/MBCFET-based 3GAE.
“N3 will be another full node stride from our N5 and will use FinFET transistor structure to deliver the best technology maturity, performance, and cost for our customers,” said Mr. Wei. “Our N3 technology development is on track with good progress. We continue to see a much higher level of customer engagement for both HPC and smartphone applications at N3 as compared with N5 and N7.”
In fact, TSMC’s claims about growing customer engagement with 3nm indirectly telegraph its high expectations for the 3nm process.
“[N3] risk production is scheduled in 2021,” said TSMC’s CEO. “The volume production is targeted in the second half of 2022. Our N3 technology will be the most advanced foundry technology in both PPA and transistor technology when it is introduced. […] We are confident that both our [N5] and [N3] will be large and long-lasting nodes for TSMC.”
GAAFETs are still a part of TSMC’s development roadmap. The largest contract chipmaker is expected to use a new kind of transistors with its ‘post-3nm’ technology (presumably N2). In fact, TSMC is in a path-finding mode for the next generations of materials and transistor structures.
“For advanced CMOS logic, TSMC’s 3nm and 2nm CMOS nodes are progressing nicely through the pipeline,” the company said in its annual report recently. “In addition, TSMC’s reinforced exploratory R&D work is focused on beyond-2nm node and on areas such as 3D transistors, new memory, and low-R interconnect, which are on track to establish a solid foundation to feed into many technology platforms.”
It is noteworthy that TSMC is expanding capacity for R&D operations at Fab 12, where advanced nodes including the 3nm and 2nm are currently being researched and developed.
Overall, TSMC is confident that its “everyone’s foundry” strategy will enable it to grow further in terms of sales, market share, and scale. The company also expects to maintain its technology leadership going forward, which is pivotal for growth.
“For the full year of 2021, we now forecast […] foundry industry growth [at] about 16%,” said Wendell Huang, CFO of TSMC, at a recent conference call with analysts and investors. “For TSMC, we are confident we can outperform the foundry revenue growth and grow by around 20% in 2021.”
The company has a strong technology roadmap and it is set to continue introducing improved leading-edge nodes every year, thus offering its customers improvements at a predictable cadence.