The Red team seems to make something for the future of its mobile computing as the US patent uncovered by the tipster @Underfox3 shows that AMD is working on a hybrid computing design. This is quite similar to ARM’s big.LITTLE architecture, wherein the high-performance cores are paired with power-efficient, low-performance cores.
This is a similar approach that most mobile mobile SoCs implement these days, helping to save battery life and be much more efficient overall. Obviously, AMD’s patent regarding hybrid computing CPU architecture makes a significant impact and raises lot of speculations in the computing space.
The patent that was filed by AMD with the US Office of Patents was of last July describing it be “A heterogeneous processor system includes a first processor implementing an Instruction Set Architecture (ISA) including a set of ISA features… lower-feature second processor is configured to execute an instruction thread by consuming less power and with lower performance than the first processor.”
If you notice the last few words of the patent, it has been stressed on the fact that there will be a lower-feature second processor which will be executing instruction thread by consuming less power and with lower performance than the first processor. The description and the diagram attached simply explains the fact AMD is trying to implement ARM’s big.LITTLE architecture.
Both these processor seem to have their own L1 Cache, but have shared access to the high-speed L2. Undoubtedly, this will be a challenging task for AMD to implement in the x86 space both in terms of hardware and software integration, but ultimately this is the future as we intend to make processors much more efficient than before.
Now, it will be interesting to see whether AMD’s BIG.little kind of architecture uses the traits of its existing Zen architecture or adapt to a completely new one. Also, how will be AMD designing this “little cores” will be a thing to notice in future and whether this kind of approach will be restricted to laptops or be implemented into desktop processors as well.
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